ASIC Digital Design, Sr. Staff Engineer

As an Analog Layout Design Engineer at Synopsys, you will play a pivotal role in developing cutting-edge layouts for next-generation DDR/HBM/UCIe IPs. Your primary responsibilities will include creating floorplans, routing, and conducting physical verifications to ensure high-quality deliverables that meet stringent quality standards within specified timelines. You will collaborate closely with design engineers to optimize layouts for performance, power efficiency, and area utilization. By implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation, you will contribute to the enhancement of the performance and reliability of semiconductor IPs. Ensuring compliance with DRC, LVS, ERC, and antenna rules will be a key part of your role to mitigate risks associated with layout design. Your expertise in deep submicron effects, floorplan techniques in CMOS, FinFET, and GAA process technologies at 7nm and below will be crucial in driving the development of high-performance silicon chips. Your problem-solving skills, along with effective communication abilities, will enable you to work efficiently with cross-functional teams and convey complex technical concepts concisely. As a valuable member of the team at Synopsys, you will contribute to the mission of leading in chip design and software security by accelerating time-to-market for innovative technologies while fostering a collaborative and inclusive work environment. Your commitment to continuous learning and professional development will be instrumental in your success within our dynamic and innovative team. Join us at Synopsys to be a part of a forward-thinking organization that values collaboration, inclusivity, and continuous improvement. We offer a comprehensive range of rewards and benefits to cater to your needs, including health, wellness, and financial benefits. Your recruiter will provide you with more details about the salary range and benefits during the hiring process.,