ASIC Digital Design, Sr. Staff Engineer Synopsys

2.0 - 6.0 years

0 Lacs

karnataka

On-site

As an Analog Layout Design Engineer at Synopsys, you will play a pivotal role in developing cutting-edge layouts for next-generation DDR/HBM/UCIe IPs. Your primary responsibilities will include creating floorplans, routing, and conducting physical verifications to ensure high-quality deliverables that meet stringent quality standards within specified timelines. You will collaborate closely with design engineers to optimize layouts for performance, power efficiency, and area utilization. By implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation, you will contribute to the enhancement of the performance and reliability of semiconductor IPs. Ensuring compliance wi...

Posted 2 weeks ago

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Analog Layout Design Engineer Synopsys (India) Private Limited

2.0 - 4.0 years

2 - 4 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

Hands-on development of layout for next-generation DDR/HBM/UCIe IPs. Creating floorplans, routing, and performing physical verifications to meet quality standards. Debugging and solving complex layout issues to ensure high-quality deliverables. Collaborating with design engineers to optimize layout for performance, power, and area. Implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation. Ensuring compliance with DRC, LVS, ERC, and antenna rules. The Impact You Will Have: Contribute to the development of cutting-edge technologies that drive the Era of Smart Everything. Enhance the performance and reliability of next-generation semiconductor IPs. Accelerate the ti...

Posted 3 months ago

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Analog layout design,Staff Engineer Synopsys (India) Private Limited

4.0 - 6.0 years

4 - 6 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

Hands-on development of layout for next-generation DDR/HBM/UCIe IPs. Solving complex problems and debugging issues effectively. Executing layout floorplanning, routing, and physical verifications to meet stringent quality requirements. Ensuring compliance with DRC, LVS, ERC, and antenna rules. Applying deep submicron effects, floorplan techniques in CMOS, FinFET, and GAA process technologies (7nm and below). Implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation. The Impact You Will Have: Enhancing the performance and reliability of Synopsys DDR/HBM/UCIe IPs. Accelerating the integration of advanced capabilities into SoCs. Reducing risk and improving time-to-ma...

Posted 3 months ago

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Analog layout design Synopsys (India) Private Limited

4.0 - 6.0 years

4 - 6 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

Hands-on development of layout for next-generation DDR/HBM/UCIe IPs. Solving complex problems and debugging issues effectively. Executing layout floor planning, routing, and physical verifications to meet stringent quality requirements. Ensuring compliance with DRC, LVS, ERC, and antenna rules. Applying deep submicron effects, floorplan techniques in CMOS, FinFET, and GAA process technologies (7nm and below). Implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation. The Impact You Will Have: Enhancing the performance and reliability of Synopsys DDR/HBM/UCIe IPs. Accelerating the integration of advanced capabilities into SoCs. Reducing risk and improving time-to-m...

Posted 3 months ago

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