9 Latchup Jobs

As a Physical Design Engineer based in Bangalore, India with over 3 years of experience, you will be responsible for various aspects of physical design for SoC using Innovus. Your key responsibilities will include floorplanning, IO ring creation, understanding ESD and latch-up requirements for foundry, and implementation strategies for placement. You will need to demonstrate expertise in hierarchical design implementation, including partitioning, push down methodologies, core/tile PG creation, and knowledge of analog components placement based on design specifications. Additionally, RDL knowledge and experience working with packaging are essential for SoC floorplan design. A critical aspect of your role will involve PV clean-up on the floorplan and ensuring compliance with Physical Verification, ESD, foundry, and analog requirements. Deep scripting knowledge is a prerequisite for this position, along with strong problem-solving capabilities, proactive attitude, hardworking nature, and excellent interpersonal skills. To qualify for this role, you must hold a Bachelor's Degree in Electrical, Electronics, or Computer Engineering. If you are looking to leverage your experience and skills in physical design within a dynamic and innovative environment, this opportunity is tailored for you.,

As a Senior Analog Layout Design Engineer at Genisup India Private Limited, a leading semiconductor and system design company based in Bangalore, you will play a crucial role in designing, developing, and modifying full custom layouts for standard cells across advanced process nodes. With a client portfolio that includes top-tier companies such as NXP, Qualcomm, and Analog Devices, we are committed to delivering innovative solutions and technical excellence in the semiconductor industry. Your responsibilities will include executing floor-planning from sub-block to chip top level, implementing hierarchical layout assembly and standard cell planning, and collaborating with design engineers to optimize layout designs for performance and manufacturability. Immediate joiners or candidates with up to a 1-month notice period are preferred for this role. Key Responsibilities: - Design, develop, and modify full custom layout designs for Standard Cells - Execute floor-planning from sub-block to chip top level - Implement hierarchical layout assembly and standard cell planning - Improve and determine methods and procedures for layout development flow to ensure efficiency and accuracy - Collaborate with design engineers to optimize layout designs for performance and manufacturability - Conduct layout verification and ensure compliance with design rules and specifications - Interpret CALIBRE DRC, LVS, ANT, EM/IR results and address issues effectively - Implement solutions for reliability concerns including ESD, Electro migration & IR, and Latch-up - Provide technical guidance and mentorship to junior layout engineers Required Qualifications: - BTech in Electronics or related field - 4+ years of hands-on experience in standard cell layout design - Experience working with FDSOI 22nm, CMOS 28nm, 40nm, 16nm ffc and beyond process nodes - Proficiency with Cadence Virtuoso Design suite - High-level expertise in layout floor-planning and hierarchical layout assembly - Strong understanding of DRC, LVS, ANT, and EM/IR verification techniques - Demonstrated knowledge of reliability issues (ESD, Electro migration, Latch-up) - Excellent analytical and problem-solving abilities - Strong communication skills and ability to mentor junior team members Preferred Skills: - Scripting experience in CSH, PERL or SKILL - Experience with advanced FinFET technology nodes - Knowledge of parasitic extraction and back-annotation - Familiarity with design for manufacturing (DFM) techniques - Experience with custom analog circuit layout optimization Join Genisup and be part of a team that is pushing the boundaries of chip design! We offer a competitive compensation package, a stimulating work environment, and a clear path for professional growth and advancement. Genisup India is an equal opportunity employer. We evaluate qualified applicants without regard to race, color, religion, gender, national origin, age, or any other protected characteristics.,

As an Analog Layout Design Engineer at Synopsys, you will play a pivotal role in developing cutting-edge layouts for next-generation DDR/HBM/UCIe IPs. Your primary responsibilities will include creating floorplans, routing, and conducting physical verifications to ensure high-quality deliverables that meet stringent quality standards within specified timelines. You will collaborate closely with design engineers to optimize layouts for performance, power efficiency, and area utilization. By implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation, you will contribute to the enhancement of the performance and reliability of semiconductor IPs. Ensuring compliance with DRC, LVS, ERC, and antenna rules will be a key part of your role to mitigate risks associated with layout design. Your expertise in deep submicron effects, floorplan techniques in CMOS, FinFET, and GAA process technologies at 7nm and below will be crucial in driving the development of high-performance silicon chips. Your problem-solving skills, along with effective communication abilities, will enable you to work efficiently with cross-functional teams and convey complex technical concepts concisely. As a valuable member of the team at Synopsys, you will contribute to the mission of leading in chip design and software security by accelerating time-to-market for innovative technologies while fostering a collaborative and inclusive work environment. Your commitment to continuous learning and professional development will be instrumental in your success within our dynamic and innovative team. Join us at Synopsys to be a part of a forward-thinking organization that values collaboration, inclusivity, and continuous improvement. We offer a comprehensive range of rewards and benefits to cater to your needs, including health, wellness, and financial benefits. Your recruiter will provide you with more details about the salary range and benefits during the hiring process.,

At Capgemini Engineering, the world leader in engineering services, you will be a part of a global team of engineers, scientists, and architects dedicated to helping the world's most innovative companies reach their full potential. From cutting-edge technologies like autonomous cars to life-saving robots, our digital and software technology experts are always thinking outside the box to provide unique R&D and engineering services across all industries. Join us for a rewarding career filled with endless opportunities where you can truly make a difference, and where no two days are ever the same. As an Analog Layout Designer, you will work independently on block-level analog layout design tasks, encompassing everything from Floorplan to Routing and Verifications. Your role will involve hands-on experience in the critical analog layout design of various blocks such as Temperature sensors, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, and Differential Amplifiers, among others. You should possess a strong proficiency in LVS/DRC debugging skills and other verifications for lower technology nodes like 14nm FinFet and below. A solid understanding of concepts such as Matching, EM, ESD, Latch-Up, Shielding, Parasitic, and short channel effects is essential for this role. Familiarity with EDA tools like Cadence VLE/VXL, PVS, Assura, and Calibre DRC/LVS is a must. You should also be able to comprehend how layout decisions impact circuit performance metrics like speed, capacitance, power, and area, and effectively implement design constraints to produce high-quality layouts. Experience with multiple tape outs will be advantageous, along with possessing good interpersonal skills and critical thinking abilities to address technical issues professionally. Excellent communication skills are vital for this role, as you will be responsible for executing layout designs in a timely manner while maintaining high quality standards. Key Skills: - Analog Layout Design - Process or technology experience: TSMC 7nm, 5nm, 10nm, 28nm, 45nm, 40nm - EDA Tools: Cadence Virtuoso Layout Editor (L, XL), Physical verification tools (DRC, LVS, Calibre) In summary, this role at Capgemini Engineering offers a dynamic opportunity to work on challenging projects, collaborate with a diverse team of professionals, and contribute to the advancement of innovative technologies across various industries. If you are someone who thrives in a fast-paced and cutting-edge environment, we welcome you to join us on this exciting journey towards engineering excellence and innovation.,

Your role at Micron Technology will involve designing and maintaining standard cells layout for new DRAM products on new technology. You will lead stdcells layout projects from initial specification definition until PPA qualified library release. Collaborating closely with the DTCO team, you will develop stdcells architecture for emerging technologies. Additionally, you will be responsible for performing layout verification tasks such as LVS/DRC/Latchup, quality checks, and documentation. Ensuring on-time delivery of block-level layouts with acceptable quality will be a key part of your responsibilities. Demonstrating leadership skills in planning, area/time estimation, scheduling, delegation, and execution to meet project schedules and milestones in a multi-project environment is essential. You will also provide guidance to junior team members in executing sub block-level layouts and reviewing their work. Contribution to effective project management and the development of new flows/methodologies to reduce stdcells manual effort and increase productivity will be part of your role. Close collaboration with the Process team, CMOS, and CAD to negotiate DRC for new technology is required. You will also work with international colleagues on developing new flows and tools for stdcells layout and design. Micron Technology, Inc. is a leading industry player in innovative memory and storage solutions, aiming to transform how information is utilized to enrich life for all. With a strong focus on customers, technology leadership, and operational excellence, Micron offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory and storage products through its Micron and Crucial brands. The innovations created by Micron's team drive the data economy, enabling advancements in artificial intelligence and 5G applications across various platforms. For further information, please visit micron.com/careers. If you require assistance during the application process or need accommodations, please reach out to hrsupport_india@micron.com. Micron strictly prohibits the use of child labor and adheres to all relevant laws, regulations, and international labor standards. Candidates are encouraged to utilize AI tools to enhance their resumes and application materials. However, all information provided must be accurate and reflect genuine skills and experiences. Misuse of AI to falsify or misrepresent qualifications will lead to immediate disqualification. A fraud alert has been issued by Micron, advising job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website.,

You have experience in Mixed-Signal layout design and hold a bachelor's degree. Your responsibilities will include working independently on block levels analog layout design from schematic, estimating the Area, optimizing Floorplan, Routing, and Verifications. You should have firsthand experience in Critical Analog Layout design of blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier, etc. It is essential to have good LVS/DRC debugging skills and other verifications for lower technology nodes like 14nm FinFet and below. You must possess a good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic, and short channel concepts. Familiarity with EDA tools like Cadence VLE/VXL, PVS, Assura, and Calibre DRC/LVS is a must. Understanding layout effects on the circuit such as speed, capacitance, power, and area is crucial. You should be able to understand design constraints and implement high-quality layouts. Multiple Tape out support experience will be an added advantage. Good people skills and critical thinking abilities to resolve issues technically and professionally are required. Excellent communication is essential, along with being responsible for timely execution with a high quality of layout design. Primary Skills: - Analog Layout - Process or technology experience: TSMC 7nm, 5nm, 10nm, 28nm, 45nm, 40nm - EDA Tools: - Layout Editor: Cadence Virtuoso L, XL - Physical verification: DRC, LVS, Calibre Secondary Skills: - IO layout,

As a Senior Staff Analog IC Design Engineer (Serial Transceiver) with over 7 years of experience, you will play a crucial role in developing sophisticated Serial Transceiver ICs for a variety of industrial applications such as factory automation, motor drives, and wireless infrastructure. Your responsibilities will span from defining specifications to overseeing production, ensuring that the ICs meet the highest standards of performance and reliability. Your expertise in Analog IC design will be key as you independently design and validate blocks like Opamps, Comparators, Schmitt Trigger, Voltage references, Current references, and Bandgap design. Additionally, your experience in High voltage Tx and Rx, Charge Pump, V2I, and top-level integration of Blocks will be instrumental in the successful completion of projects. Collaboration with layout engineers on IC floorplan and integration of analog, ESD, and digital components will be essential to ensure a seamless design process. Your strong communication skills will be put to use as you work with Systems, Marketing, and Applications team to define product specifications and drive validation processes. Your role will also involve participating in design reviews, layout reviews, and providing regular design updates through documentation and presentations. You will implement standard design validation methodologies to ensure product reliability and yield meet industry standards. Post-silicon debugs, system characterization support, and guiding new hires and junior designers within the team will also be part of your responsibilities. Experience in Rx and Tx designs for Transceivers or IOs, High voltage Design, Analog buffers, Bandgap reference, ESD/Latchup, and Si debug will be crucial for success in this role. Your understanding of Analog design principles, process technologies, device behavior, and reliability issues will be highly valuable. In summary, as a Senior Staff Analog IC Design Engineer, you will be at the forefront of developing cutting-edge Serial Transceiver ICs, ensuring they meet the highest standards of performance, reliability, and functionality. Your technical expertise, passion for innovation, and strong communication skills will be key to your success in this role.,

We are looking for highly skilled Physical Verification Engineers to join our team. The ideal candidates will have extensive experience in physical verification tasks such as DRC, LVS, and parasitic extraction using tools like Mentor Graphics Calibre. You will be working on cutting-edge technologies and collaborating with cross-functional teams to ensure seamless tapeouts and compliance with foundry design rules. Your main responsibilities will include implementing Physical Verification with a focus on hard macro/core finishing activities. You must have led and been primarily responsible for physical verification checks, fixing, and sign-off. It is essential to have an excellent understanding of the Physical Verification flow, with experience in analyzing and debugging DRC, ERC, LVS, DFM, Antenna, PERC, and Rule deck issues primarily using the Calibre tool. Additionally, a deep understanding of ESD, latch-up, etc., is required. You will be responsible for owning and executing Physical Verification activities at the Top/Block level. Collaborating closely with the PD team to address their PV issues and suggest solutions is a key aspect of the role. Working with CAD team to refine existing flows/methodologies and resolve issues is also part of the job scope. Experience in IO, Bump planning, RDL routing Strategy, and developing/implementing timing and logic ECOs are considered advantageous. Knowledge of tools like Innovus/FC for DRC fixing, Python, PERL/TCL scripting, and the ability to plan, work independently, and coordinate with cross-functional teams are essential. Closing sign off DRC based on PNR markers is a plus. The ideal candidate should have experience with physical verification checks such as DRC, LVS, Antenna, ERC, PERC, ESD, etc. Experience with PnR tools like ICC/Innovus and understanding sign-off PDV tools like PDK Concepts, SVRF, Calibre, and ICV is required. A good overall understanding of the Custom IC design flow, layouts, and backend tool flow would be beneficial. Hands-on experience with tools like Innovus/Fusion Compiler, Tech lef is preferable. People management, floorplanning, power planning, and PDN experience are considered a big plus. The ability to script in TCL/PERL and familiarity with physical convergence in PnR tools are also advantageous. In return, we offer a competitive salary, performance-based bonuses, comprehensive benefits package including health insurance, retirement plans, and paid time off. Additionally, you will have opportunities for professional development and career growth in a collaborative and innovative work environment with state-of-the-art facilities.,

You will be responsible for the layout of Analog and mixed-signal modules in CMOS and Power Technologies, with a specific focus on DC-DC converters for power management ICs. This includes designing Analog and mixed-signal system resource blocks such as POR, Bandgap, LDO, Oscillator, amplifier, and power FET. You will also be involved in chip floor-planning, pad ring layout, power busing, bonding, and tape-out activities. Your role will require a deep understanding of layout verification processes like DRC, LVS, Latch-up, and Electro-migration. Additionally, you will collaborate closely with designers to define block layout requirements, match patterns, and ensure signal integrity. To qualify for this position, you should hold a Diploma, Bachelor's, or Master's Degree in Electrical/Electronic Engineering, Physics, or a related field with 7 to 10 years of relevant experience. Your expertise should include Analog and mixed-signal layout, especially in CMOS and Power Technologies. Strong analytical skills and a comprehensive understanding of Analog Layout are essential for this role. Familiarity with power switch layout, electro-migration, and thermal analysis would be advantageous. Proficiency in computer-aided design tools and methodologies is also required to excel in this position.,