15 Latchup Jobs

As a Senior Analog Layout Engineer at Xeedo Technologies working for Micron Technology, you will be responsible for designing analog and custom digital layout blocks in advanced CMOS technologies. Your primary role will involve performing full physical verification using Mentor Graphics Calibre tools, ensuring first-pass silicon success, and collaborating with global design teams for successful project execution and tape-outs. Key Responsibilities: - Design and develop analog and custom digital layout blocks - Perform full physical verification using Mentor Graphics Calibre - Interpret circuit schematics to optimize layouts - Plan, estimate, and track layout tasks - Collaborate with cross-fu...

You will be responsible for working on high speed DDRIO in locations like Bangalore, Hyderabad, and Noida. Your key responsibilities will include: - Having work experience in high speed transreceiver - Prior work experience in high speed TX and RX - Knowledge of ESD and Latchup - Dealing with layout related issues - Demonstrating strong debug capability To qualify for this role, you should have: - At least 4 years of experience in the field - A degree in BE/B-Tech/ME/M-Tech in Electronics and Communication, Electrical Engineering, or a related field.,

As a Standard Cells Layout Design Engineer at Micron Technology, you will play a crucial role in designing and maintaining standard cells layout for new DRAM products on cutting-edge technology. Your responsibilities will include: - Leading standard cells layout projects from initial spec definition to PPA qualified library release - Collaborating closely with the DTCO team to develop standard cells architecture for emerging technologies - Performing layout verification tasks such as LVS, DRC, Latchup, quality checks, and documentation - Ensuring on-time delivery of block-level layouts with acceptable quality - Demonstrating leadership skills in planning, area/time estimation, scheduling, de...

You will be responsible for the layout of Analog and mixed-signal modules in CMOS and Power Technologies, with a specific focus on DC-DC converters for power management ICs. This includes designing Analog and mixed-signal system resource blocks such as POR, Bandgap, LDO, Oscillator, amplifier, and power FET. You will also be involved in chip floor-planning, pad ring layout, power busing, bonding, and tape-out activities. Your role will require a deep understanding of layout verification processes like DRC, LVS, Latch-up, and Electro-migration. Additionally, you will collaborate closely with designers to define block layout requirements, match patterns, and ensure signal integrity. - Hold a D...

As a CAD Staff Engineer at Micron Technology, Inc., you will be working in a collaborative, production support role evaluating, improving EDA and debugging both in-house and commercial Electronic Design Automation (EDA) tools and flows for the physical layout, verification, and design of CMOS integrated circuits. You will work closely with the Layout design teams to increase their productivity and work efficiency. Responsibilities And Tasks Include, But Not Limited To: - Work closely with memory layout teams and solve their daily challenges and provide complete solutions for the future. - Proactively identify problem areas for improvement, propose, and develop innovative solutions. - Develop...

As an experienced Analog Layout design engineer, you are expected to be innovative, collaborative, meticulous, and curious. Key Responsibilities: - Layout of basic digital and analog building blocks using analog transistor level components. - Layout of analog macros, power pads, and input/output pads using the above blocks. - Working closely with Analog designers in floorplanning; power grid and signal flow planning. - Physical and electrical verification include DRC, LVS, EM/IR, ERC, PERC Latch up, and PERC ESD. - Creation of blackbox models for other groups in the design flow. Preferred Experience: - Must have detailed knowledge of CMOS circuit theory. - Must have the ability to communicat...

As a Physical Design Engineer based in Bangalore, India with over 3 years of experience, you will be responsible for various aspects of physical design for SoC using Innovus. Your key responsibilities will include floorplanning, IO ring creation, understanding ESD and latch-up requirements for foundry, and implementation strategies for placement. You will need to demonstrate expertise in hierarchical design implementation, including partitioning, push down methodologies, core/tile PG creation, and knowledge of analog components placement based on design specifications. Additionally, RDL knowledge and experience working with packaging are essential for SoC floorplan design. A critical aspect ...

As a Senior Analog Layout Design Engineer at Genisup India Private Limited, a leading semiconductor and system design company based in Bangalore, you will play a crucial role in designing, developing, and modifying full custom layouts for standard cells across advanced process nodes. With a client portfolio that includes top-tier companies such as NXP, Qualcomm, and Analog Devices, we are committed to delivering innovative solutions and technical excellence in the semiconductor industry. Your responsibilities will include executing floor-planning from sub-block to chip top level, implementing hierarchical layout assembly and standard cell planning, and collaborating with design engineers to ...

As an Analog Layout Design Engineer at Synopsys, you will play a pivotal role in developing cutting-edge layouts for next-generation DDR/HBM/UCIe IPs. Your primary responsibilities will include creating floorplans, routing, and conducting physical verifications to ensure high-quality deliverables that meet stringent quality standards within specified timelines. You will collaborate closely with design engineers to optimize layouts for performance, power efficiency, and area utilization. By implementing layout matching techniques, ESD, latch-up, EMIR, DFM, and LEF generation, you will contribute to the enhancement of the performance and reliability of semiconductor IPs. Ensuring compliance wi...

At Capgemini Engineering, the world leader in engineering services, you will be a part of a global team of engineers, scientists, and architects dedicated to helping the world's most innovative companies reach their full potential. From cutting-edge technologies like autonomous cars to life-saving robots, our digital and software technology experts are always thinking outside the box to provide unique R&D and engineering services across all industries. Join us for a rewarding career filled with endless opportunities where you can truly make a difference, and where no two days are ever the same. As an Analog Layout Designer, you will work independently on block-level analog layout design task...

Your role at Micron Technology will involve designing and maintaining standard cells layout for new DRAM products on new technology. You will lead stdcells layout projects from initial specification definition until PPA qualified library release. Collaborating closely with the DTCO team, you will develop stdcells architecture for emerging technologies. Additionally, you will be responsible for performing layout verification tasks such as LVS/DRC/Latchup, quality checks, and documentation. Ensuring on-time delivery of block-level layouts with acceptable quality will be a key part of your responsibilities. Demonstrating leadership skills in planning, area/time estimation, scheduling, delegatio...

You have experience in Mixed-Signal layout design and hold a bachelor's degree. Your responsibilities will include working independently on block levels analog layout design from schematic, estimating the Area, optimizing Floorplan, Routing, and Verifications. You should have firsthand experience in Critical Analog Layout design of blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier, etc. It is essential to have good LVS/DRC debugging skills and other verifications for lower technology nodes like 14nm FinFet and below. You must possess a good understanding of Matching, EM, ESD, Latch-Up, Shie...

As a Senior Staff Analog IC Design Engineer (Serial Transceiver) with over 7 years of experience, you will play a crucial role in developing sophisticated Serial Transceiver ICs for a variety of industrial applications such as factory automation, motor drives, and wireless infrastructure. Your responsibilities will span from defining specifications to overseeing production, ensuring that the ICs meet the highest standards of performance and reliability. Your expertise in Analog IC design will be key as you independently design and validate blocks like Opamps, Comparators, Schmitt Trigger, Voltage references, Current references, and Bandgap design. Additionally, your experience in High voltag...

We are looking for highly skilled Physical Verification Engineers to join our team. The ideal candidates will have extensive experience in physical verification tasks such as DRC, LVS, and parasitic extraction using tools like Mentor Graphics Calibre. You will be working on cutting-edge technologies and collaborating with cross-functional teams to ensure seamless tapeouts and compliance with foundry design rules. Your main responsibilities will include implementing Physical Verification with a focus on hard macro/core finishing activities. You must have led and been primarily responsible for physical verification checks, fixing, and sign-off. It is essential to have an excellent understandin...

You will be responsible for the layout of Analog and mixed-signal modules in CMOS and Power Technologies, with a specific focus on DC-DC converters for power management ICs. This includes designing Analog and mixed-signal system resource blocks such as POR, Bandgap, LDO, Oscillator, amplifier, and power FET. You will also be involved in chip floor-planning, pad ring layout, power busing, bonding, and tape-out activities. Your role will require a deep understanding of layout verification processes like DRC, LVS, Latch-up, and Electro-migration. Additionally, you will collaborate closely with designers to define block layout requirements, match patterns, and ensure signal integrity. To qualify...