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Analog Mixed Signal Verification Engineer

Analog Mixed Signal Verification Engineer

Vhunt4u

4 - 9 years

60 - 65 Lacs

taiwan bengaluru

Posted:None| Platform:

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Skills Required

system verilog verification engineering analog mixed uvm

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Work from Office

Job Type

Full Time

Job Description

B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering.
Expertise in mixed signal IC verification / design experience Expertise in analog and mixed-signal circuit topologies Define verification plan based on product specifications and application use-casesDevelop top-level AMS test benches using Cadence / System Verilog / UVM frameworkSimulate and validate verification plan use-casesWork with design team to debug and support issuesManage bug trackingCreate automated regression flowsDocument and organize regression resultsConduct AMS waveform reviewmaster the full AMS verification process. Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations Preferred resources with valid regional work permit

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Analog Mixed Signal Verification Engineer