AMS Layout

You are an Experienced Layout Engineer sought by ACL Digital for their Bangalore location. Your role involves working with AMS/IO Memory Layout, specifically focusing on Lower nodes from TSMC and ESD Blocks. As a candidate, you are expected to have a Bachelor's or Master's Degree with 4 - 12 years of Analog Layout experience. Additionally, you should possess demonstrated leadership skills, including hiring, nurturing talent, leading project execution, and client/stakeholder management for at least 3 years. Your key responsibilities will include: - Full-custom circuit layout/verification and RC extraction experience - Experience in advanced technology node under TSMC - 32nm/28nm/16nm/14nm/7nm. 5nm/3nm is preferable - Experience with EMIR analysis, ESD, antenna, and related layout solutions - Good understanding of advanced semiconductor technology process and device physics - Familiarity with Cadence Virtuoso environment and various industry physical verification tools (DRC, LVS, DFM, etc) - Experience in one or more of the following areas is preferable: Mixed-signal/analog/high-speed layout, e.g., SerDes, ADC/DAC, PLL, etc Qualifications required for this role are: - Bachelor's or Master's Degree - 4 - 12 years of Analog Layout experience - Excellent communication skills - Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment - Programming skills, automation, and circuit design background are a plus If you are interested in this position, you can share your resume or refer someone by contacting karthick.v@acldigital.com.,