7 Emir Analysis Jobs

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. As an experienced 3DIC and Advanced Packaging Physical Implementation Engineer with a strong background in backend design, particularly in deep sub-micron technology, you will be responsible for various tasks including 3DIC design partition, floor planning, IP placement, TSV placement, and power grid planning and design. Your expertise will be crucial in optimizing for power and thermal performance, generating 3D stacking, hybrid bonding pad, and ubump map, designing AP RDL, conducting Place and Route, and managing the tape out process. Your role will also involve collaborating with the IP implementation group to develop different views and enable the design flow, providing IP and chiplet pre-sales P&R mockup design and post-sales support, and interfacing with Synopsys EDA tool and internal CAD group. The impact of your work will drive innovation in 3DIC and advanced packaging technologies, enhance power and thermal efficiency in chip designs, and contribute to the successful implementation of Synopsys IP, test chips, and chiplets. To excel in this role, you should have a minimum of 10+ years of relevant experience in physical design, deep sub-micron technology large scale chip tape out experience from RTL to GDS, proficiency in EMIR analysis and DRC/LVS tools, and knowledge of 3DIC and 2.5D advanced packaging, silicon interposer, and bridge. Experience in power analysis and Custom Compiler is a plus. You will be part of a global, highly skilled, and supportive team focused on driving advancements in 3DIC and advanced packaging technologies. Our team collaborates closely with various departments to develop innovative solutions and optimize design flows, ensuring the successful implementation of Synopsys tools and technologies in customer projects.,

We are searching for enthusiastic and dedicated design engineers to become a part of our Central Engineering Group and join a distinguished team responsible for developing foundation IP for AI products. This includes memory compilers, logic cells, and various custom macros utilizing cutting-edge process technology. Multiple positions are available across all experience levels. Responsibilities include designing and constructing memory or circuit blocks at the gate or transistor level, simulating and analyzing circuit designs using transistor level simulators, extracting layouts and conducting post-layout simulations and verifications, floorplanning for physical implementation and integrating layout components, incorporating characterization flow for timing and power information extraction, developing scripts for automating characterization flow, simulations, and verifications, specifying and verifying various behavioral and physical memory models, documenting design specifications, behavioral descriptions, and timing diagrams, as well as assisting in specifying silicon test plans and correlating silicon to simulation data. Preferred skills include a strong grasp of transistor level circuit behavior and device physics, understanding of signal integrity analysis, EM/IR analysis, and reliability analysis, proficiency in running simulators, writing automation scripts, and adeptness with tools, familiarity with memory behavioral and physical models, expertise in memory circuit design, comprehension of DFT schemes and chip level integration, effective communication, interpersonal, and leadership skills, self-motivation, multitasking abilities, a passion for tackling intricate problems, and an eagerness to learn.,

At Cadence, we are committed to hiring and developing leaders and innovators who aspire to create an impact in the technology industry. We are currently seeking a Lead Application Engineer for our GCS team based in Bangalore or Noida. As a pivotal leader in electronic design, Cadence leverages over 30 years of computational software expertise to deliver cutting-edge software, hardware, and IP solutions that bring design concepts to life. Our customers, who are among the most innovative companies worldwide, rely on us to deliver exceptional electronic products across various dynamic market applications. Joining Cadence offers you the opportunity to work with state-of-the-art technology in an environment that fosters creativity, innovation, and impact. Our employee-friendly policies prioritize the well-being and career development of our employees, providing ample opportunities for learning and growth. Our inclusive "One Cadence - One Team" culture celebrates diversity and equity, enabling us to innovate, grow, and succeed with our customers. As a Lead Application Engineer in the GCS Organization for MSA (Multiphysics System Analysis), your role involves collaborating with Cadence customers globally to offer post-sales technical consultation for IC level Power System analysis products. You will work closely with customers to resolve complex issues, help them leverage the latest tools, and guide them in implementing software within their design methodologies. This role allows you to broaden and deepen your technical knowledge, gain exposure to industry best practices, and contribute high-impact knowledge content. Additionally, you will have the opportunity to contribute to the development of key technology solutions and provide feedback to enhance product offerings. You will work in a supportive and flexible environment, where your success is a collective effort and passion for technology and innovation drives us forward. **Job Responsibilities:** - Provide technical support for Voltus product from the Multiphysics System Analysis (MSA) toolset, focusing on productivity and customer satisfaction - Support multiple tools/methods, requiring general domain knowledge and business experience - Assist in creating impactful knowledge content in the MSA domain - Work independently at Cadence or customer facilities to deliver quality results according to schedule requirements - Work on problems of moderate scope that may require analysis of situations, data, or tool problems **Qualifications:** - Bachelors Degree in Electrical/Electronics/Electronics and Communication/VLSI Engineering with 5-7 years of related experience - OR Masters with 3-4 years of related experience - OR PhD with 1 year of related experience **Experience And Technical Skills Required:** - 3-7 years of relevant industry experience in EMIR analysis, PDN analysis with digital signoff tools, and Digital Physical implementation - Strong background in Digital logic Design, CMOS logic Design, Power IR drop analysis, Circuit Design and Analysis, Digital and Behavioral simulation fundamentals - Proficiency in debugging Low power and multiple power domain analysis for chip power integrity sign-off - Understanding of Digital design toolsets of Cadence (Genus/Innovus/Tempus/Conformal) and hardware description languages like VHDL, Verilog, System Verilog - Knowledge of TCL, Perl, or Python scripting **Behavioral Skills Required:** - Strong written, verbal, and presentation skills - Ability to establish a close working relationship with both customer peers and management - Creative problem-solving skills and ability to explore unconventional solutions - Effective collaboration across functions and geographies - Commitment to raising the bar while maintaining integrity Join us at Cadence, where we are dedicated to tackling meaningful challenges and pushing the boundaries of what is possible in technology. Let's solve problems that others can't.,

At Cadence, we are committed to hiring and developing leaders and innovators who are passionate about making a significant impact in the technology industry. Our company has a rich history of over 30 years of expertise in computational software, and we continue to lead in electronic design by applying our Intelligent System Design strategy to bring design concepts to life through software, hardware, and IP solutions. Our diverse range of customers includes some of the most innovative companies worldwide, creating electronic products for various dynamic market applications. The Cadence Advantage: - You will have the opportunity to work with cutting-edge technology in a creative and innovative environment that encourages you to make a real impact. - Our employee-friendly policies prioritize the physical and mental well-being of our employees, career development, learning opportunities, and recognition of success. - We foster a culture of diversity, equity, and inclusion through our "One Cadence - One Team" approach to drive innovation, growth, and success with our customers. - There are multiple avenues for learning and development tailored to individual needs and interests. - You will collaborate with a dedicated and talented team that is passionate about serving our customers and communities. As a Lead Application Engineer in the GCS Organization for the MSA (Multiphysics System Analysis), you will work closely with Cadence customers globally to provide post-sales technical consultation for IC level Power System analysis products. Your role involves helping customers understand and resolve complex issues, utilize the latest tool capabilities, and implement software in their design methodologies. You will gain extensive technical knowledge, exposure to industry design practices, and contribute impactful knowledge content. Responsibilities: - Provide technical support for the Voltus product within the Multiphysics System Analysis toolset, focusing on productivity and customer satisfaction. - Support various tools and methods for customers, developing domain knowledge and business experience. - Contribute to creating high-quality knowledge content in the MSA domain. - Independently deliver quality results at Cadence or customer facilities according to schedule requirements. - Work on problems of moderate scope that may require analysis of situations, data, or tool issues. Qualifications: - Bachelor's Degree in Electrical/Electronics/Electronics and Communication/VLSI Engineering with 5-7 years of related experience, or Master's with 3-4 years of experience, or PhD with 1 year of experience. Experience and Technical Skills Required: - 3-7 years of industry experience in EMIR analysis, PDN analysis, digital signoff tools, and Digital Physical implementation. - Strong background in Digital logic Design, CMOS logic Design, Power IR drop analysis, Circuit Design, and Analysis. - Proficiency in debugging Low power and multiple power domain analysis for chip power integrity sign-off. - Familiarity with Cadence digital design toolsets and hardware description languages like VHDL, Verilog, System Verilog. - Knowledge of scripting languages like TCL, Perl, or Python. Behavioral Skills Required: - Strong written, verbal, and presentation skills. - Ability to build close relationships with customers and management. - Willingness to explore unconventional solutions to achieve goals. - Effective collaboration across functions and geographies. - Commitment to integrity and continuous improvement. Join us in our mission to tackle challenging problems and make a difference where others cannot.,

You will be responsible for Analog Layout tasks with a focus on AMS/IO Memory, Full-custom circuit layout/verification, and RC extraction. Your role will involve working with lower nodes from TSMC, specifically focusing on ESD Blocks. As an Experienced Layout Engineer at ACL Digital, you should hold a Bachelor's or Master's Degree with a minimum of 4 years of Analog Layout experience. In this position, you will need to demonstrate leadership skills acquired over at least 3 years, including hiring, nurturing talent, leading project execution, and managing clients and stakeholders effectively. Your excellent communication skills will be crucial, along with a hands-on approach to your work. An in-depth understanding of advanced semiconductor technology processes and device physics is essential for this role. Experience in full-custom circuit layout/verification and RC extraction is required, with a preference for expertise in areas such as Mixed signal/analog/high-speed layout (e.g., SerDes, ADC/DAC, PLL). Familiarity with the Cadence Virtuoso environment and various physical verification tools (DRC, LVS, DFM) is also desirable. You should have prior experience working with advanced technology nodes under TSMC (32nm/28nm/16nm/14nm/7nm), with exposure to 5nm/3nm being an added advantage. Additionally, experience with EMIR analysis, ESD, antennas, and related layout solutions will be beneficial. Your ability to collaborate with a global team, strong learning competency, self-motivation, and flexibility to work in diverse areas will be crucial for success in this role. Programming skills, automation experience, and a background in circuit design would be considered advantageous. If you meet these qualifications and are excited about this opportunity, please share your interest or refer suitable candidates to karthick.v@acldigital.com.,

Provide technical support for Voltus product from the Multiphysics System Analysis (MSA) toolset of Cadence products with focus on productivity, and customer satisfaction Support multiple tools/methods for customer requiring general domain knowledge and developing business experience Assist in creation of high quality and impactful knowledge content in MSA domain Work independently at Cadence or customer facilities to deliver quality results according to schedule requirements Work on problems of moderate scope that may require analysis of situations, data or tool problems Qualifications Bachelor s Degree in; Electrical / Electronics / Electronics and Communication / VLSI Engineering with 5-7 years related experience OR Masters with 3-4 years of related experience OR PhD with 1 years of related experience Experience and Technical Skills required 3-7 years relevant industry experience in EMIR analysis, PDN analysis with digital signoff tools and Digital Physicalimplementation as designer or methodology/flow expert Strong background in Digital logic Design, CMOS logic Design, Power IR drop analysis, Circuit Design and Analysis, Digital and Behavioral simulation fundamentals related to IC and Package Design Debugging of Low power and multiple power domain analysis for chip power integrity sign-off. Understanding of Digital design toolsets of Cadence (Genus / Innovus / Tempus / Conformal); knowledgeable of at least 50% of a given flow; detailed knowledge in one CDN tool, learning others; ability to analyze customers environment and evaluate appropriate support solutions; learning competitive tools/technologies Must have excellent debugging skills and ability to separate out the critical issues from trivial ones. Ability to solve interface level problems emanating from IC Implementation side and System analysis side. Ability to debug Timing and thermal issues in relation to IR and EM is a plus Good understanding of Hardware description languages like VHDL, Verilog, System Verilog. Knowledge on TCL, Perl or Python scripting. Behavioral skills required Must possess strong written, verbal and presentation skills Ability to establish a close working relationship with both customer peers and management Explore what s possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity

B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering. Expertise in Analog Layout design Expertise in planar technology node / higher node 180 nm is mandatory Expertise in EMIR analysis, ESD, antenna and related layout solutions Knowledge of advanced technology nodes (7nm & below) Good understanding of advanced semiconductor technology process and device physics Full-custom circuit layout/verification and RC extraction experience Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC,LVS,DFM) Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations Preferred resources with valid regional work permit Location - Bangalore, Beijing, Taiwan, Vietnam