AMS Layout

You will be responsible for Analog Layout tasks with a focus on AMS/IO Memory, Full-custom circuit layout/verification, and RC extraction. Your role will involve working with lower nodes from TSMC, specifically focusing on ESD Blocks. As an Experienced Layout Engineer at ACL Digital, you should hold a Bachelor's or Master's Degree with a minimum of 4 years of Analog Layout experience. In this position, you will need to demonstrate leadership skills acquired over at least 3 years, including hiring, nurturing talent, leading project execution, and managing clients and stakeholders effectively. Your excellent communication skills will be crucial, along with a hands-on approach to your work. An in-depth understanding of advanced semiconductor technology processes and device physics is essential for this role. Experience in full-custom circuit layout/verification and RC extraction is required, with a preference for expertise in areas such as Mixed signal/analog/high-speed layout (e.g., SerDes, ADC/DAC, PLL). Familiarity with the Cadence Virtuoso environment and various physical verification tools (DRC, LVS, DFM) is also desirable. You should have prior experience working with advanced technology nodes under TSMC (32nm/28nm/16nm/14nm/7nm), with exposure to 5nm/3nm being an added advantage. Additionally, experience with EMIR analysis, ESD, antennas, and related layout solutions will be beneficial. Your ability to collaborate with a global team, strong learning competency, self-motivation, and flexibility to work in diverse areas will be crucial for success in this role. Programming skills, automation experience, and a background in circuit design would be considered advantageous. If you meet these qualifications and are excited about this opportunity, please share your interest or refer suitable candidates to karthick.v@acldigital.com.,