VLSI MBIST Engineer

1. VLSI MBIST Engineer

Experience: 4-8 Years

Work location: Bangalore

We are seeking a skilled VLSI MBIST Engineer with approximately 4 years of experience, specialized in Memory Built-In Self-Test (MBIST) methodologies. The ideal candidate will have hands-on experience with Synopsys SMS tool and be proficient in MBIST pattern generation, fault simulation, and test development for various embedded memories in ASIC/SoC designs

Key Responsibilities:

• Develop and implement MBIST algorithms and test patterns for embedded memories (SRAM, DRAM, ROM, CAM) using Synopsys SMS tool.
• Create MBIST test infrastructure and collaborate with design teams to integrate MBIST macros into SoC designs.
• Perform fault modeling, fault simulation, and analysis to ensure high fault coverage and test quality.
• Validate MBIST patterns through simulation and silicon validation.
• Debug MBIST failures at both pre-silicon and post-silicon stages and provide root cause analysis.
• Work closely with RTL designers, physical design, and test teams to optimize MBIST architecture and test flows.
• Generate MBIST test reports, documentation, and provide design-for-test (DFT) reviews.
• Stay updated with latest MBIST methodologies and industry trends.

Required Skills & Qualifications:

• Bachelors/Master’s degree in Electronics, Electrical Engineering, VLSI, or related field.
• Minimum 4 years of experience in MBIST engineering for ASIC/SoC designs.
• Strong knowledge of MBIST architectures, memory testing algorithms, and fault models.
• Hands-on experience with Synopsys SMS tool for MBIST pattern generation and validation.
• Familiarity with other DFT tools and methodologies is a plus.
• Proficient in scripting languages such as TCL, Perl, or Python for automation of MBIST flows.
• Good understanding of digital design and RTL coding (Verilog/SystemVerilog).
• Experience with simulation tools (ModelSim, VCS, etc.) and testbench development.
• Strong analytical and problem-solving skills with attention to detail.
• Good communication skills and ability to work in a team environment.

Preferred Skills:

• Experience with other memory test tools or DFT tools like Tessent.
• Knowledge of ATPG and other DFT methodologies.
• Exposure to silicon bring-up and failure analysis.
• Familiarity with industry standards such as IEEE 1149.1 (JTAG), IEEE 1500.

  Role & responsibilities

Preferred candidate profile