4 Fault Simulation Jobs

The Opportunity We&aposre looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrows future by accelerating the critical data communication at the heart of our digital world from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. Role Summary: As a DFT engineer at Alphawave Semi, you will be working on end-to-end Custom Silicon Design cycle, from DFT-architecture planning to delivering qualified Si parts to our customers. You will be using some the best industry-standard tools and Alphawave specific workflows to implement full chip level advanced Scan and MBIST insertion, verification, and pattern generation. Your role will involve collaborating closely with customers, working hand-in-hand with RTL/PD teams and supporting Test/Product Engineering teams. What you&aposll do : Develop and implement comprehensive DFT architectures, collaborating on early planning stages. Serves as the primary point of contact for DFT-related inquiries and leads the implementation efforts, ensuring alignment with customer requirements. Implement scan and MBIST using industry-standard EDA tools. Develop and execute DFT verification plans (pattern generation, fault simulation). Collaborate with cross-functional teams to resolve DFT-related issues. Document DFT architecture and verification results. What you&aposll need: Proven leadership in complete DFT implementation and team guidance. Experience driving DFT implementation on large designs. Silicon debug experience related to DFT. BTech/MTech in EE or related field, 15+ years DFT experience. Nice to have: Familiarity with advanced DFT techniques (e.g. In-system test, SSN, multi-die testing). Tool and methodology development related to DFT. '' We have a flexible work environment to support and help employees thrive in personal and professional capacities " As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process. Show more Show less

As a Senior DFT Engineer at Arms Solutions group DFT team in Bengaluru, India, you will play a crucial role in implementing DFT for test-chips and hard-macros to validate Arm's soft IP power, performance, area, and functionality within the context of a SoC. You will collaborate closely with RTL, Verification, Physical Implementation, and Test engineering teams throughout the project lifecycle, from early investigation to tape-out and silicon test/characterization on ATE. Your responsibilities will include architecting, implementing, and validating innovative DFT techniques on test-chips and hard-macros. You will insert DFT logic into SoC-style designs at the RTL and Synthesis gate levels, validate features, and generate ATE-targeted test patterns for silicon testing. Collaboration with front-end design, verification, synthesis, place-and-route, static-timing-analysis, and test/debug teams will be essential for successful project delivery. The ideal candidate for this role is a Senior DFT Engineer with 8+ years of experience in Design for Test, proficient in Verilog RTL coding, scripting languages like TCL and/or Perl, and Unix/Linux environments. Core DFT skills required include Scan compression and insertion, Memory BIST, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate-level verification, and silicon debug. Experience with Siemens, Cadence, and/or Synopsys DFT and simulation tools is desirable. Nice to have skills include familiarity with IEEE standards, Synthesis, Static Timing Analysis, and Siemens DFT tools. The ability to work collaboratively in a team and independently, coupled with innovative thinking and time management skills, will be valued in this role. In return, you will have the opportunity to work with industry experts, competitive compensation, great benefits, and flexible working hours. Arm values building extraordinary teams and is committed to creating an inclusive work environment. Accommodations during the recruitment process can be arranged by contacting accommodations@arm.com. Arm also supports hybrid working arrangements to promote high performance and personal wellbeing. The specifics of hybrid working for each role will be shared upon application, ensuring a balance between flexibility and meeting business needs. Arm is dedicated to equal opportunities and creating a diverse and inclusive workplace. Join Arm's DFT team in Bengaluru and be part of a dynamic environment where innovation and collaboration thrive!,

VLSI MBIST Engineer Experience: 4-8 Years Work location: Bangalore Job Description: We are seeking a skilled VLSI MBIST Engineer with approximately 4 years of experience, specialized in Memory Built-In Self-Test (MBIST) methodologies. The ideal candidate will have hands-on experience with Synopsys SMS tool and be proficient in MBIST pattern generation, fault simulation, and test development for various embedded memories in ASIC/SoC designs Key Responsibilities: Develop and implement MBIST algorithms and test patterns for embedded memories (SRAM, DRAM, ROM, CAM) using Synopsys SMS tool. Create MBIST test infrastructure and collaborate with design teams to integrate MBIST macros into SoC designs. Perform fault modeling, fault simulation, and analysis to ensure high fault coverage and test quality. Validate MBIST patterns through simulation and silicon validation. Debug MBIST failures at both pre-silicon and post-silicon stages and provide root cause analysis. Work closely with RTL designers, physical design, and test teams to optimize MBIST architecture and test flows. Generate MBIST test reports, documentation, and provide design-for-test (DFT) reviews. Stay updated with latest MBIST methodologies and industry trends. Required Skills & Qualifications: Bachelors/Master’s degree in Electronics, Electrical Engineering, VLSI, or related field. Minimum 4 years of experience in MBIST engineering for ASIC/SoC designs. Strong knowledge of MBIST architectures, memory testing algorithms, and fault models. Hands-on experience with Synopsys SMS tool for MBIST pattern generation and validation. Familiarity with other DFT tools and methodologies is a plus. Proficient in scripting languages such as TCL, Perl, or Python for automation of MBIST flows. Good understanding of digital design and RTL coding (Verilog/SystemVerilog). Experience with simulation tools (ModelSim, VCS, etc.) and testbench development. Strong analytical and problem-solving skills with attention to detail. Good communication skills and ability to work in a team environment. Preferred Skills: Experience with other memory test tools or DFT tools like Tessent. Knowledge of ATPG and other DFT methodologies. Exposure to silicon bring-up and failure analysis. Familiarity with industry standards such as IEEE 1149.1 (JTAG), IEEE 1500. Role & responsibilities Preferred candidate profile

Job Description : We are looking for a VLSI MBIST Engineer with strong expertise in Memory Built-In Self-Test (MBIST) methodologies for ASIC/SoC designs. The ideal candidate should have hands-on experience using Synopsys SMS tool and a solid understanding of MBIST test development, pattern generation, and fault simulation. Key Responsibilities : Develop and implement MBIST algorithms and test patterns for embedded memories (SRAM, DRAM, ROM, CAM) Use Synopsys SMS tool for MBIST pattern generation and validation Perform fault modeling, fault simulation, and fault coverage analysis Integrate MBIST macros into SoC designs in collaboration with RTL and physical design teams Debug MBIST issues in pre- and post-silicon stages Document MBIST flows, generate test reports, and provide support for DFT reviews Stay updated on industry trends and best practices in MBIST and memory testing Required Skills : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, VLSI, or related fields 4+ years of experience in MBIST implementation and validation Strong experience with Synopsys SMS tool Proficiency in scripting languages like TCL, Perl, or Python Good knowledge of Verilog/SystemVerilog and digital design fundamentals Familiarity with simulation tools like VCS, ModelSim Preferred Skills : Experience with DFT tools such as Tessent Knowledge of ATPG, JTAG (IEEE 1149.1), and IEEE 1500 standards Exposure to silicon bring-up and failure analysis