9 Fault Simulation Jobs

Job Title: DFT Practice Head Location: Bengaluru, India Experience: 12 to 16 years Position Overview The DFT Practice Head will lead the organization's Design for Test (DFT) competency, overseeing strategic direction, technology advancement, and team excellence. This leadership role will be responsible for building and strengthening DFT capabilities to support complex ASIC and SoC programs, ensuring quality, performance, and delivery excellence. Key Responsibilities Define and implement the overall DFT strategy, methodology, and best practices across projects and teams. Lead and mentor a team of DFT engineers, fostering a culture of technical excellence and continuous learning. Drive executi...

We're looking for an engineer with a minimum of 6 years of experience in the DFT domain, including at least 4 years specializing in Memory Built-In Self-Test (MBIST) methodologies. The ideal candidate will have hands-on experience with MBIST insertion at the Block/SoC level. Proficient in MBIST pattern generation, fault simulation, and test development for various embedded memories. The engineer should also have worked on pattern simulations with and without SDF (Timing). Possess strong experience with Mentor tools for MBIST implementation and pattern generation. Additionally, having knowledge of memory grouping at the SoC level. Experience in shared bus-based MBIST insertion for advanced no...

Meta is hiring ASIC DFT Engineers within our Infrastructure organization to work on Design for Test (DFT) methodologies, implementation, and verification to build best-in-class System on a Chip (SOC) and IP for data center applications. The role offers the opportunity to apply your expertise in Design for Testability (DFT) methodologies and IP/SOC implementation. You will leverage and further develop your understanding of Siemens/Synopsys DFT EDA tools and IEEE standards (1149, 1500, 1687). ASIC Implementation, DFT Engineer Responsibilities: Develop and implement DFT strategies for data center scale large/disaggregated SOCs, considering factors such as fault coverage, test time, and in-syste...

Position Overview We are seeking a highly motivated & passionate for safety, Functional Safety Architect to join our semiconductor architecture design team. In this role, you will own the device safety architecture and lead the efforts to achieve safety goals by developing technical safety concepts including safety mechanisms derived from safety analyses; and allocating decomposed safety requirements to each IP sub-blocks for next-generation semiconductor devices. You will collaborate with architects, IP owners, RTL design engineers, physical design, firmware and verification teams to deliver critical safety collaterals ensuring end goal of achieving successful functional safety certificatio...

Job Description Arms Solutions group DFT team implements DFT for test-chips and hard-macros to prove Arm&aposs soft IP power, performance, area, and functionality within the context of a SoC using the latest DFT techniques and process technologies. We closely collaborate with RTL, Verification, Physical Implementation, and Test engineering teams throughout the life cycle of a project, from an early investigation stage all the way through tape-out and silicon test/characterization on ATE. Responsibilities Architect, Implement, and validate innovative DFT techniques on test-chips and hard-macros. Insert DFT logic into SoC-style designs at the RTL level and at the Synthesis gate level, validate...

The Opportunity We&aposre looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrows future by accelerating the critical data communication at the heart of our digital world from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. Role Summary: As a DFT engineer at Alphawave Se...

As a Senior DFT Engineer at Arms Solutions group DFT team in Bengaluru, India, you will play a crucial role in implementing DFT for test-chips and hard-macros to validate Arm's soft IP power, performance, area, and functionality within the context of a SoC. You will collaborate closely with RTL, Verification, Physical Implementation, and Test engineering teams throughout the project lifecycle, from early investigation to tape-out and silicon test/characterization on ATE. Your responsibilities will include architecting, implementing, and validating innovative DFT techniques on test-chips and hard-macros. You will insert DFT logic into SoC-style designs at the RTL and Synthesis gate levels, va...

VLSI MBIST Engineer Experience: 4-8 Years Work location: Bangalore Job Description: We are seeking a skilled VLSI MBIST Engineer with approximately 4 years of experience, specialized in Memory Built-In Self-Test (MBIST) methodologies. The ideal candidate will have hands-on experience with Synopsys SMS tool and be proficient in MBIST pattern generation, fault simulation, and test development for various embedded memories in ASIC/SoC designs Key Responsibilities: Develop and implement MBIST algorithms and test patterns for embedded memories (SRAM, DRAM, ROM, CAM) using Synopsys SMS tool. Create MBIST test infrastructure and collaborate with design teams to integrate MBIST macros into SoC desig...

Job Description : We are looking for a VLSI MBIST Engineer with strong expertise in Memory Built-In Self-Test (MBIST) methodologies for ASIC/SoC designs. The ideal candidate should have hands-on experience using Synopsys SMS tool and a solid understanding of MBIST test development, pattern generation, and fault simulation. Key Responsibilities : Develop and implement MBIST algorithms and test patterns for embedded memories (SRAM, DRAM, ROM, CAM) Use Synopsys SMS tool for MBIST pattern generation and validation Perform fault modeling, fault simulation, and fault coverage analysis Integrate MBIST macros into SoC designs in collaboration with RTL and physical design teams Debug MBIST issues in ...