UVM Verification Team Lead

Job Description

Organization Details: CENTUM T&S, headquartered in France, is a business unit of Centum Electronics Group (Around 1000Cr turnover organization) offering a wide range of electronic and embedded systems design engineering services to international customers to help them realize complex products and sub systems. It includes design, development, qualification, value engineering, testbench design & manufacturing and many more services. Centum T&S has established its India operations in North Bengaluru, known as Centum T&S Pvt Ltd (CTS), formerly known as Centum Adeneo India Pvt Ltd. CTS is working with many top companies like Airbus, Thales, Hitachi Energy, GE, ABB, DANA, Alstom, etc., The ideal candidate is a self-motivated, multi-tasker, and demonstrated team-player. You will be responsible for the delivery of the items assigned to you with quality and should interact with cross functional team and resolve the problem. You should excel in working with global stakeholders and have outstanding communication and leadership skills and report to the Project Manager. What You'll Do: Lead the UVM verification team, focusing on high-performance digital designs. Manage UVM based verification strategies for FPGA designs, System Verilog, ensuring compliance with industry standards. Collaborate with cross-functional teams to achieve project milestones. Develop and execute FPGA verification plans using advanced methodologies like UVM. UVM Verification environment development Perform verification environment using UVM methodologies, create verification environments for high-speed protocols like Multi gigabit ethernet interface, AXI Stream, AXI Lite, verification IP development, Knowledge of encryption/decryption standards like AES, knowledge of PCI express, DDR4 interface on FPGAs and its verification environment creation using UVM Mentor junior engineers and oversee team deliverables. Work closely with FPGA design engineers to ensure seamless integration. Qualifications : BE/MTech in Electronics and communications engineering 6+ years of experience in UVM verification. Very strong knowledge of SystemVerilog and usage of latest FPGAs Proficiency in UVM, and scripting languages like Python or Perl. Knowledge of Siemens Questa UVM simulator, writing custom scripting for the tools (like TCL, FuseSoC, etc), analyze and debug the environment by waveforms. Familiarity with high-speed interfaces like PCIe, Multi giga bit Ethernet, and DDR4. Strong leadership and communication skills.