UVM Verification Lead

As a UVM Verification Lead at the company, you will be responsible for leading verification projects, developing test plans, writing test cases, creating verification environments, and performing code reviews. Your role will involve coordinating with design teams to understand and verify the functionality of design blocks, debugging failures, and ensuring that verification objectives and timelines are met. Key Responsibilities: - Lead verification projects - Develop test plans and write test cases - Create verification environments - Perform code reviews - Coordinate with design teams - Debug failures - Ensure verification objectives and timelines are met Qualifications Required: - Experience with UVM and SystemVerilog - Proficiency in developing test plans and writing test cases - Skilled in creating verification environments and performing code reviews - Strong understanding of digital design and hardware description languages - Excellent debugging skills and the ability to coordinate with design teams - Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field - Good communication and team collaboration skills - Experience in a leadership role and handling multiple projects is a plus,