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Trainee - Design

Trainee - Design

Tessolve

1 - 3 years

3 - 5 Lacs

Bengaluru

Posted:1 day ago| Platform:

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Skills Required

Automation ASIC VHDL JTAG DFT VLSI SOC Verilog Perl Python

Work Mode

Work from Office

Job Type

Full Time

Job Description

About Tessolve

Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide a full turnkey solution for silicon bring-up, validation, and characterization. We are a preferred partner for several top-tier semiconductor companies and are constantly expanding our engineering capabilities.

We are looking for a passionate and skilled

DFT Engineer

with 1 3 years of experience in Design for Test to join our VLSI team in Bangalore. The ideal candidate will be involved in DFT architecture, implementation, and validation across various SoC/ASIC projects.

Job Title:

DFT Engineer

Experience:

1 to 3 Years

Location:

Bangalore

Key Responsibilities

Implement and verify DFT features such as scan insertion, boundary scan (JTAG), MBIST/Logic BIST.
Perform ATPG and fault simulation.
Support pattern generation and ATE pattern bring-up.
Collaborate with RTL designers, backend teams, and validation engineers to ensure high-quality DFT implementation.
Debug and resolve issues in scan/MBIST/ATPG.
Prepare DFT reports and documentation for sign-off and customer delivery.

Required Skills

Strong knowledge of DFT concepts like scan, ATPG, BIST, boundary scan, and test compression.
Hands-on experience with tools like Synopsys DFT Compiler, TetraMAX/SpyGlass DFT, or Cadence Modus/Genus.
Good understanding of RTL design (Verilog/VHDL) and simulation.
Exposure to scripting (TCL, Perl, Python) for automation.
Basic knowledge of STA and timing constraints related to DFT paths.

Preferred Qualifications

Bachelors/Master s degree in Electronics/Electrical/Computer Engineering.
Familiarity with ATE platforms (like Teradyne/Advantest) is a plus.
Strong problem-solving and analytical skills.
Ability to work collaboratively in a team-oriented environment.

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