Staff Engineer, Verification

Your Team, Your Impact

What You Can Expect

Essential Responsibilities (not limited to):

• Responsible for understanding the logic, develop hitlist, verification environment, testcases etc. , required for verifying the logic, individually
• Implement verification methodologies for testbench development
• Develop scripts required for running simulations and regressions and debug fails
• Document the verification plan and verification documentation
• Plan functional coverage/code coverage, analyze and improve coverage
• Review and update verification environment and testcases
• Report, track and close logic issues
• Work and communicate effectively with global team
• Work with designers and FW engineers to enable better verification

What Were Looking For

Essential qualifications:

• Must have good digital logic understanding and fundamentals of digital design.
• Candidate must have excellent skills in digital logic verification and hardware description language (VHDL or Verilog),
• Strong knowledge in object oriented programming using languages such as SystemVerilog
• Must have hands on experience in hardware verification methodologies such as UVM or OVM,
• Must be familiar with verification test planning and coverage driven verification closure, Verification strategies for directed and randomized testing and assertions
• Must have good experience in using simulation tools and proficiency in simulation debug techniques.
• Strong knowledge / experience in building the verification environment from specification and should have spec to hardware bring-up experience.
• Must have hands on knowledge on test-bench development and automation, bug tracking, and regression mechanisms
• Should be able to act as the team lead to determine methods and procedures on new assignments and coordinate activities of other team members to ensure successful project completion.

Preferred skills:

• Experience in High Speed SerDes, clock data recovery based PHYs, Asynchronous clock domain crossing verification.
• IP architecture and verification knowledge
• Experience in scripting languages such as Perl
• Gatelevel simulation and AMS simulation knowledge
• Experience with Linux operating system
• Experience with Cadence or any other industry tools
• Should be a good team player
• Good communication skills and quick learning ability.
• Knowledge of standard configuration management system like CVS or SVN

Education:

• Bachelor s degree in Computer Science, Electrical Engineering or related fields and 5-8 years of related professional experience.
• Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 4-6 years of experience.