Staff Engineer, RTL & SoC Interconnect Design Engineer

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Responsibilities:

• Design and develop RTL for SoC interconnects (NoCs) across multiple product lines using protocols like AMBA AXI, ACE, and CHI.
• Lead and handle RTL design teams, including mentoring engineers from diverse technical backgrounds.
• Collaborate with architecture and platform teams to define interconnect requirements, including performance, power, safety (ASIL-B), and coherency.
• Drive SoC-level planning including address mapping, cross-trigger definition, debug infrastructure, and system coherency support.
• Work with physical design (PD), synthesis, and DV teams to close timing and ensure quality of RTL delivery.
• Enable power-aware design by collaborating with power and clocking teams on strategies like root clock gating and partial/full power collapse.
• Develop productivity tools in Python for design rule checking (DRC) and interface validation.
• Coordinate SoC-level execution by interfacing with IP and subsystem teams to align schedules, resolve late feature changes, and handle deliverables.
• Support silicon bring-up, debug, and post-silicon performance analysis through detailed simulation and system-level integration.
• Maintain SoC planning elements such as die walk, geometry dimensions, and critical issue processes.

Required Skills and Experience :

• 10+ years of experience in RTL design, SoC interconnect development, and subsystem integration.
• Deep expertise in bus protocols such as AMBA AXI, ACE, CHI, and coherency mechanisms in modern SoCs.
• Confirmed experience handling and mentoring design teams in both technical and leadership capacities.
• Strong knowledge of interconnect power optimization, safety features (ASIL-B), and performance tuning.
• Hands-on experience with industry-standard EDA tools for simulation, synthesis, lint, and power analysis.
• Proficiency in scripting and automation using Python.
• Demonstrated ability to work across functions from architecture to PD to software and systems in global engineering environments.

Nice To Have Skills and Experience :

• Experience with Arteris FlexNoC or similar commercial interconnect IPs.
• Familiarity with hardware security concepts and access protection mechanisms.
• Exposure to FPGA flows, debugging, and client platform support.
• Working knowledge of safety-critical design flows in automotive and video analytics systems.
• Background in chip-level planning, die management, and SoC convergence processes.

In Return:

• Partner and dedication towards or customers
• Collaborate and communication
• Originality and resourcefulness
• Team and personal development
• Impact and influence

Equal Opportunities at Arm