Company
Qualcomm India Private Limited
Job Area
Engineering Group, Engineering Group > Hardware Engineering
General Summary
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.
Minimum Qualifications
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
Job Title:
Signoff Static Timing Analysis CAD Engineer
Experience Level
: 12 Years
Location
: Bangalore
Job Summary
We are looking for a CAD STA Signoff Engineer to support and enhance static timing analysis flows and methodologies for timing signoff.The role involves working closely with design teams to ensure timing closure across multiple corners and modes, and maintaining robust CAD infrastructure for STA.The position requires Signoff Static Timing Analysis (STA) knowledge, with CAD development skills to define and develop tools and methodologies for accuracy, compute, in close collaboration with EDA Vendors and Snapdragon Design teams.Qualcomm is using leading edge internal and EDA technologies in the Signoff domain, including pioneering in genAI/ML, and enabling the latest STA features to reduce conservatism in Signoff.
Key Responsibilities
- Develop, maintain, and support STA signoff flows using tools like Tempus, PrimeTime or equivalent.
- Collaborate with design teams to debug timing issues.
- Automate STA workflows using Tcl, Python, or Perl to improve efficiency and consistency.
- Ensure correlation between implementation and signoff tools.
- Methodology improvement: Drive STA methodology improvements to enhance efficiency, productivity, and timing correlation for diverse Mobile, Compute, AI, IoT Snapdragon chips.
- Generate and review timing reports for tapeout readiness.
Required Skills
- 12 years of experience in STA and CAD flow development.
- Strong understanding of timing concepts: setup/hold, OCV analysis, hierarchical STA, SI/noise analysis.
- Experience with timing tools (e.g., Synopsys PrimeTime, Cadence Tempus).
- Proficiency in scripting languages (Tcl, Python, Perl).
- Familiarity with SDC constraints, Library modeling (LVF, CCS, NLDM), and timing closure strategies.
- Good communication and collaboration skills.
Preferred Qualifications
- Bachelor's or master's degree in electrical engineering, VLSI, or related field.
- Exposure to STA, signal integrity, and noise analysis.
- Experience with programming languages like Pyhon, Tcl and Perl.
Applicants
: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [HIDDEN TEXT] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
