Sr Staff Engineer, Physical Verification

Physical verification engineer for SOC/blocks

Key Responsibilities

Physical verification for SOCs, cores, and blocks, including DRC, LVS, ERC, ESD, DFM, and tapeout processes.

Address critical design and execution challenges associated with physical verification and sign-off.

Have a comprehensive understanding of physical verification and sign-off workflows and methodologies.

Partner with PNR engineers to achieve sign-off at various stages of the design process.

Proficient in physical verification for SoC/full-chip and block-level processes, including DRC, LVS, ERC/PERC, DFM, OPC, and tape out.

Experience: 7-15Y

Comprehensive experience and understanding of all stages of the IC design process from RTL to GDS2.

Skilled in troubleshooting LVS issues at the chip level, particularly with complex analog-mixed signal IPs.

Familiar with low-power design techniques, including level shifters, isolation cells, power domains/islands, and substrate isolation.

Experienced in physical verification of I/O rings, corner cells, seal rings, RDL routing, bumps, and other full-chip components.

Capable of developing sign-off methodologies/flows and providing support to larger teams.

Knowledge of ERC rules, PERC rules, and ESD rules is a valuable asset.

Experience in floor planning is a plus

Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you.