SOC/Subsystem Verification

5 - 10 years

25 - 40 Lacs

Posted:1 day ago| Platform: Naukri logo

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Work Mode

Hybrid

Job Type

Full Time

Job Description


JD2 SoC Verification Engineer (Pre-Silicon DV with C Experience)

Location

SoC Verification Engineers

Key Responsibilities

  • End-to-end SoC/IP verification Test plan creation, TB development, regressions, coverage closure.
  • Work on

    debug subsystem verification

    at SoC level, collaborating with RTL, architecture, and software teams.
  • Bring-up/debug SoC testcases, including power/clock/reset flows.
  • Develop

    C/Assembly diagnostics

    for SoC-level scenarios.
  • Drive coverage, assertion-based verification, debug failures, and closure.
  • Work independently and also mentor junior engineers if required.

Required Skills

  • Strong in

    System Verilog, UVM

    , Assertions, Coverage.
  • Good

    SoC level DV experience

    (not just IP-level).
  • C/Assembly programming exposure

    (mandatory).
  • Debugging at SoC level power/reset/boot/debug flows.
  • Familiarity with

    ARM-based SoCs

    is a big plus.
  • Scripting: Python/Perl/Shell for automation.
  • Strong debugging skills with simulators (VCS, Questa, Verdi, etc.).

Email

JD3 – Debug Subsystem Verification Engineer (ARM Coresight)

Location

Debug Subsystem Verification Engineers

Key Responsibilities

  • End-to-end

    debug subsystem verification

    at SoC level.
  • Define Verification Plans, testcase bring-up, debug & trace flow validation.
  • Validate

    ARM Coresight Debug & Trace IPs

    – Trace, DAPROM, Device Discovery, CXDT.
  • Work closely with architecture and SW teams for debug requirements.
  • Develop and debug

    C-based diagnostics

    for debug and trace flows.
  • Drive

    GLS, Coverage closure, Assertion-based verification

    .

Required Skills

  • Strong SoC DV experience

    (debug/trace focus).
  • Hands-on with

    ARM Coresight Debug & Trace Architecture

    .
  • Good understanding of

    CXDT, Trace Unformatter, DAPROM, Device Discovery concepts

    .
  • Proficient in

    System Verilog + UVM

    .
  • Strong

    C programming skills

    (mandatory).
  • Exposure to GLS, Low Power/UPF simulation is a plus.
  • Tools: VCS/Questa, Verdi, ARM DS-5, Trace tools.

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