Job
Description
As a full-time SOC physical implementation engineer, you will be responsible for all aspects of physical design functions, from unit level to chip level. Your role will involve tasks such as P&R, timing, floorplan, clocking, electrical analysis, and power optimization. Your key responsibilities will include: - Owning block level design from RTL-to-GDSII and driving synthesis, floor-planning, place & route, timing closure, and signoff. - Working closely with Micro-architects to conduct feasibility studies and explore performance, power & area (PPA) tradeoffs for design closure. - Developing physical design methodologies and customizing recipes across various implementation steps to optimize PPA. - Collaborating with a multi-functional engineering team to implement and validate physical design by running all signoff flows such as Timing, Power, EM/IR, PDV. To excel in this role, you should have: - Knowledge of using synthesis, place & route, analysis, and verification CAD tools. - Familiarity with logic & physical design principles to drive low-power & higher-performance designs. - Proficiency in scripting in languages like Unix, Perl, Python, and TCL. - Good understanding of device physics and experience in deep sub-micron technologies. - Knowledge of Verilog and SystemVerilog. - Excellent problem-solving skills, written and verbal communication, organization skills, and self-motivation. - Ability to work effectively in a team and deliver results under aggressive schedules. Moreover, you are required to have a PhD, Masters Degree, or Bachelors Degree in a technical subject area. Please note that artificial intelligence tools may be used to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist the recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.,
