SMTS PERFORMANCE VERIFICATION ENGINEER

THE ROLE:

The person will be part of AMD's Server SoC Performance Validation team. This team is part of AMD's global Server SoC Performance teams and plays a critical role in next generation AMD Server SoC design. Involves having deep understanding of existing AMD X86 SoC architecture/microarchitecture including CPU/ Cache Hier, Memory Subsystem and IO subsystem; debugging performance issues of RTL, giving feedback to design team for latest gen SoC in pre-silicon and emulation environment.

We highly encourage people with a creative bent of mind and with a natural ability to dive into the details. This team is a perfect place for people who can understand the present and envision the future. If you find yourself to be a person who wants to go that extra mile to refine an existing process and also understands the opportunities to make it better, if you are the one who has innovative ideas in your brain waiting to find a proper stage to come out, we can offer you the perfect ground for that.

THE PERSON:

Should have excellent inter-personal, communication skills and ability to work in a fast-paced exciting environment. Continuous learning has always been the moto in this ever changing industry. An ideal person for this role should be a self-learner and always ready to upgrade his/her skills to stay abreast with the technology. The team looks for superstars but also believes in nurturing you into one. Collaboration is the key to success. Ideal candidate should learn at a great pace, deliver what is expected and also share your learning in the team to help the overall growth. It's always We before Me in the team

KEY RESPONSIBILITIES:

• Responsible for building infrastructure for performance verification and verify performance of X86 SoC. Performance verification at full chip env involves Core Subsystem ,Memory Subsystem and IO Subsystem perf verification.
• Writing specific targeted tests to measure the performance of the Server SoC

• In coordination with Perf architects,driving tuning of performance results to meet product bounding box

• Involves having a deep understanding of SoC micro-architecture and triaging performance issues in RTL and simulator Skillset
• Debug triage of failures from simulation and emulation environment for SoC or sub level regressions.
• Writing automatized triages in Perl/Ruby and creating tools using perl/ruby or AMD verification methodology (primarily in C++) to enhance the functional debug and triage process.
• On a need basis, work on Post-Si bug recreation.
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PREFERRED EXPERIENCE:

• Experience: 10-18 years experience in processor/ASIC performance correlation.
• Experience in micro-architecture testing for modern high-performance processors.
• Experience in writing tests and building infrastructure that tests performance of modern processors.
• Experience in application performance analysis Programming/Scripting Skills C, C++, Perl, Python.
• Solid background and understanding of Digital Design, RTL design , improving model performance and Processor Architecture Strong troubleshooting, analytical and debug skills.
• Prior experience in performance correlation of Processor subsystems is a plus.
• Excellent knowledge of computer architecture with relevantresearch and project work or industry experience
• Strong programming skills (C/C++ and assembly)
• Basic knowledge of Verilog
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ACADEMIC CREDENTIALS:

• Bachelors/Masters in Computer Science/Electrical/Electronics Engineering with relevant course and research work