Senior High-Speed Analog Designer

Review SerDes standards to define analog sub-block specifications Architect and refine circuits for optimal power, area, and performance Propose and implement verification strategies using advanced simulator features Supervise physical layout to manage parasitics, stress, and process variations Present simulation results to peers and customers for validation Document design methodologies, test plans, and circuit features Provide electrical characterization guidance and suggest post-silicon updates The Impact You Will Have: Innovate in high-speed analog IC design for next-gen SerDes IP Ensure efficient, reliable analog designs meeting stringent specs Influence architectural strategies and best practices in analog design Enable successful integration of analog blocks into customer systems Strengthen the R&D team through knowledge sharing and technical leadership Drive product performance and power efficiency across SerDes solutions What You'll Need: BE with 8+ years or MTech with 6+ years of experience in Electrical/Computer Engineering Strong expertise in transistor-level CMOS analog design Design experience with one or more SerDes sub-circuits (e.g., PLL, RX, TX) Awareness of ESD design strategies and reliability (EM, IR, aging) Familiarity with custom digital logic and high-speed paths Proficiency in SPICE simulation, schematic/layout tools, and design verification Experience with Verilog-A modeling and scripting (TCL, Perl, Python, MATLAB)