14 Spice Simulation Jobs

The ideal candidate for this position should have 1-2 years of experience in AMS design verification. You will be responsible for developing Verilog/VerilogA/VerilogAMS models for signal and power management modules to support top-level verification. Experience in full chip DV would be an added advantage. You will contribute to the development of the Full-Chip AMS-DV plan and own significant pieces of this verification process. It is essential to have the ability to drive best practices in the field of AMS-DV. In this role, you will work independently to identify bugs and resolve them formally with cross-functional teams. An understanding of analog power IPs will be beneficial as it can help in the debugging of chip-level AMS bugs. Proficiency in using tools such as Cadence Virtuoso, Spectre & Spice simulation, Incisive, and AMS simulators is required. You will utilize RTL and Gates+SDF, including process variation in back-annotated timing simulations. This will involve verifying chip-level timing between analog and digital circuits, parasitic resistance and capacitance, and using Assura parasitic extraction tools. Experience in constrained-random stimulus and auto-checking verification environments, especially constrained-random analog stimulus, is desired. The successful candidate should be able to work efficiently in a fast-paced product development environment. You will manage bug tracking and RTL code coverage, collaborate with design and systems teams to address bugs as they arise, and review digital and analog designs to provide guidance on Design for Verification architecture and features during chip development.,

As an AMS Verification Engineer, you will be responsible for working on Analog Mixed-Signal (AMS) Verification for SoCs, subsystems, and IPs. Your role will involve hands-on experience with AMS simulation environments using tools such as Cadence, Synopsys, or Mentor. It is essential to have a solid understanding of analog and mixed-signal circuits, including comparators, op-amps, switched-cap circuits, ADCs/DACs, current mirrors, charge pumps, and regulators. Your expertise in Verilog, Verilog-A, Verilog-AMS, and Verilog-D for behavioral modeling will be crucial for block-level and chip-level AMS verification. This includes top-level testbench development, self-checking testbenches, and regression suites. Exposure to SystemVerilog (SV) and UVM from an AMS perspective will be considered a plus. Proficiency in scripting languages such as Python, Perl, TCL, or SKILL for automation is required. You should be fluent with Cadence Virtuoso-based analog design flow, encompassing schematic capture, simulator/netlist configuration, and SPICE simulation. Your ability to extract, analyze, and document simulation results and present findings in technical reviews is highly valued. Furthermore, familiarity with test plan development, AMS modeling, and verification methodologies is essential. You will also be involved in supporting post-silicon validation and correlating measurement data with simulations. As a valued team member, you should be team-oriented, proactive, and able to contribute effectively in a multi-site development environment.,

As a skilled professional in Standard Cell Library Development, you will leverage your hands-on experience and expertise to contribute effectively to the characterization processes. Your solid understanding of CMOS and FinFET technologies will be key in ensuring the success of the projects at hand. Additionally, exposure to Verilog modeling will be advantageous in this role, although it is not mandatory. Your role will require strong debugging and problem-solving skills specifically related to cell design, SPICE simulation, and characterization. This will enable you to address challenges effectively and ensure the quality of the developed libraries. Proficiency in EDA tools is essential for this position. Experience with tools such as Cadence Virtuoso, Calibre, HSPICE, and other industry-standard simulation and characterization tools will be beneficial in carrying out your responsibilities efficiently. Overall, your role will be crucial in contributing to the development of Standard Cell Libraries, and your expertise will play a vital part in the success of the projects.,

Responsibilities: * Design power electronics solutions using Spice simulation and PCB layout. * Collaborate with electrical engineers on electrical power systems and converters. Assistive technologies Marriage & childbirth gifts Free meal Employee state insurance Maternity policy Annual bonus Referral bonus Leave encashment Gratuity Provident fund

Review SerDes standards to define analog sub-block specifications Architect and refine circuits for optimal power, area, and performance Propose and implement verification strategies using advanced simulator features Supervise physical layout to manage parasitics, stress, and process variations Present simulation results to peers and customers for validation Document design methodologies, test plans, and circuit features Provide electrical characterization guidance and suggest post-silicon updates The Impact You Will Have: Innovate in high-speed analog IC design for next-gen SerDes IP Ensure efficient, reliable analog designs meeting stringent specs Influence architectural strategies and best practices in analog design Enable successful integration of analog blocks into customer systems Strengthen the R&D team through knowledge sharing and technical leadership Drive product performance and power efficiency across SerDes solutions What You'll Need: BE with 8+ years or MTech with 6+ years of experience in Electrical/Computer Engineering Strong expertise in transistor-level CMOS analog design Design experience with one or more SerDes sub-circuits (e.g., PLL, RX, TX) Awareness of ESD design strategies and reliability (EM, IR, aging) Familiarity with custom digital logic and high-speed paths Proficiency in SPICE simulation, schematic/layout tools, and design verification Experience with Verilog-A modeling and scripting (TCL, Perl, Python, MATLAB)

Review SerDes standards to develop analog sub-block design specifications Define and refine circuit architectures to meet power, area, and performance goals Devise design and verification strategies leveraging advanced simulation tools Supervise physical layout to manage parasitics, device stress, and variability Present simulation data for internal and customer-facing reviews Document design methodologies, features, and test strategies Support electrical characterization and propose post-silicon design updates The Impact You Will Have: Drive innovation in high-speed analog circuit design for SerDes IP Ensure optimal trade-offs in power, area, and performance Enhance reliability and manufacturability of analog sub-blocks Support successful integration of SerDes IP into customer solutions Contribute to best practices in analog design and simulation within the team Influence product development strategies with expert design knowledge What You'll Need: BE with 8+ years or MTech with 6+ years of relevant experience in Electrical/Computer Engineering Strong expertise in transistor-level CMOS circuit design and analog design fundamentals Experience in designing SerDes sub-circuits like PLLs, TX, RX, CDR, etc. Understanding of ESD protection, custom digital design, and high-speed logic Familiarity with reliability concerns such as EM, IR drop, and aging Proficient with schematic/layout tools and SPICE-based simulators Knowledge of Verilog-A for behavioral modeling and scripting in TCL, Perl, Python, or MATLAB

Conceptualizing, designing, and productizing state-of-the-art circuit components for SLM monitors realized through ASIC design flow. Designing on-chip Process, Voltage, Temperature, glitch, and Droop monitors for monitoring silicon biometrics. Developing statistical simulation methodologies and collaborating with the layout team to achieve optimal design solutions. Characterizing designed custom cells and deploying new circuits into test chips for post-silicon characterization. Creating new cells and updating existing ones through collaboration with architects and Physical Design engineers. Conducting pre and post-layout simulations and characterizations across various design corners to ensure reliability and aging requirements. The Impact You Will Have: Accelerating the integration of next-generation intelligent in-chip sensors and analytics into technology products. Optimizing performance, power, area, schedule, and yield of semiconductor lifecycle stages. Enhancing the reliability and differentiation of products in the market with reduced risk. Driving innovation in custom circuit design methodologies and tools. Contributing to the development of industry-leading SLM monitors and silicon biometrics solutions. Collaborating with cross-functional teams to ensure the successful deployment of advanced technologies. What You'll Need: BS or MS degree in Electrical Engineering with 5+ years of relevant industry experience. Strong custom design experience, including specification, circuit design description, and schematics. Proficiency with circuit design and simulation tools, IC design CAD packages from any EDA vendor. Sound understanding of SPICE simulator concepts and simulation methods. Experience with statistical design methodologies like generating and analyzing Monte-Carlo results.

- New Product Development - Develop new & innovative spice products from concept to commercialization - Manage a portfolio of spice development projects - Standardize recipes, specifications of spices, blends & seasonings - Handle customer queries

Design oriented and forward-looking thought process Sound knowledge of custom Analog/AMS design techniques, implementation and verification B.Tech. or M.Tech. degree in Electrical Engineering with 5+ years of relevant industry experience or Phd with relevant experience. Awareness of full custom layout techniques Exposure to advanced process challenges, including ESD and Reliability Exposure to architecture, design and verification of PVT, Oscillators, Bandgap, PLLs, LDOs, ADCs, Amplifiers, PHYs and other Mixed-signal blocks Excellent teamwork, communication, mentoring, and interpersonal skills with both internal teams and external customers Preferred skills : Strong custom design experience - specification, circuit design description and schematics Hands on experience with circuit design & simulation tools, IC design CAD packages - from any EDA vendor Strong understanding of SPICE simulator concepts and simulation methods Familiar with circuit simulation tools like PrimeSim, FineSim, HSPICE or similar Must have prior experience with Custom Compiler or equivalent schematic & Layout editor tools Experience with statistical design methodology like generating and analyzing Monte-Carlo results Awareness of post-layout extraction & simulation, testing in conjunction with silicon validation Demonstrated technical expertise in the productization of advanced technologies

Reviewing Die, package, and PCB physical layout designs Modeling, simulating, and verifying high-speed interface performance against specifications Participating in the improvement of SI/PI methodology flows Collaborating and networking with other teams on task-oriented projects Independently driving SI/PI research and development activities Ensuring designs meet stringent performance, power, and size requirements The Impact You Will Have: Enhance the performance and reliability of high-speed interfaces Contribute to the development of cutting-edge technology in chip design Improve SI/PI methodology flows, increasing efficiency and accuracy Foster collaboration and innovation across globally distributed teams Drive research and development initiatives to stay ahead in the industry Support Synopsys mission to lead in the Era of Pervasive Intelligence What You ll Need: Bachelors or Masters degree in Electrical or Electronics Engineering Minimum of 5 years of relevant experience Proficient in Transmission line theory and time/frequency-domain analysis Experienced with SPICE and familiar with 3D field solvers Conversant with working of DDR and PCIe/Ethernet interfaces Good verbal and written English communication skills Experience in scripting languages such as Python and TCL is a plus Familiarity with both Windows and Linux operating system

* Diagnose problem, understand customer requirements and propose new enhancements for product improvement. * Support Benchmarking/customer engagements * Perform internal testing along release cycles * Prepare usage specification for new projects * Prepare and Deliver Product training/presentation/demos Qualifications and Experience * 5+ year Transistor level circuit simulation or support experience. * Experience in Standard Cell design, IO Cell design or Custom Cell design. * Experience in Std Cell/IO Cell/Custom Cell characterization * Solid understanding of SPICE simulation with industry-standard simulators * Knowledge of simulation environment integration is desirable. * Excellent communication and presentation skills, problem solving, and project management skills as well as ability to interface with customers and developers are essential. * Education: BSEE or equivalent with 5+ years (or MS/Ph.D. with 3+ years) of relevant experience

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a highly skilled and experienced Analog Design Engineer with a passion for developing cutting-edge technology With a strong foundation in Electrical or Computer Engineering, you have honed your expertise in transistor-level circuit design and are adept at working with high-speed analog integrated circuits Your deep understanding of CMOS design fundamentals and familiarity with various SerDes sub-circuits make you an invaluable asset to any team You thrive in collaborative environments, working seamlessly with cross-functional teams of analog and digital designers Your meticulous approach ensures optimal power, area, and performance targets are met, and your innovative design strategies push the boundaries of what is possible You are not only technically proficient but also possess excellent communication and documentation skills, allowing you to effectively share your ideas and results with peers and customers Your proactive attitude and problem-solving abilities make you a go-to person for post-silicon design updates and electrical characterization In summary, you are a seasoned professional ready to take on the challenges of high-speed analog integrated circuit design in the latest FinFET process nodes, What Youll Be Doing: Review SerDes standards to develop analog sub-block specifications, Identify and refine circuit architectures to achieve optimal power, area, and performance targets, Propose design and verification strategies that efficiently use simulator features to ensure the highest quality design, Oversee physical layout to minimize the effect of parasitics, device stress, and process variation, Present simulation data for peer and customer review, Document design features and test plans, Consult on the electrical characterization of your circuit within the SerDes IP product, Propose solutions for post-silicon design updates, The Impact You Will Have: Drive innovation in high-speed analog integrated circuit design, Ensure optimal performance, power efficiency, and area utilization of our products, Contribute to the development of industry-leading SerDes IP, Enhance the reliability and quality of our analog sub-blocks, Support the successful integration of SerDes IP into customer products, Foster collaboration and knowledge sharing within the R&D team, Influence design strategies and best practices within the organization, What Youll Need: BE with 8+ years of relevant experience or MTech with 6+ years of relevant experience in Electrical Engineering or Computer Engineering, In-depth familiarity with transistor-level circuit design and sound CMOS design fundamentals, Detailed design experience with at least one, and familiarity with several other SerDes sub-circuits, Awareness of ESD issues and circuit techniques for addressing them, Familiarity with custom digital design and high-speed logic paths, Knowledge of design for reliability, including EM, IR, and aging considerations, Experience with tools for schematic entry, physical layout, and design verification, Hands-on experience with physical layout of high-speed circuits is a plus, Proficiency with SPICE simulators and simulation methods, Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture, Experience with scripting languages such as TCL, Perl, C, Python, or MATLAB is desired, Who You Are: Collaborative and able to work effectively in a team environment, Detail-oriented with a strong focus on quality and reliability, Proactive problem-solver with innovative design strategies, Excellent communicator with strong documentation skills, Adaptable and able to thrive in a fast-paced, dynamic environment, The Team Youll Be A Part Of: You will be part of a fast-growing analog and mixed-signal R&D team dedicated to developing high-speed analog integrated circuits in the latest FinFET process nodes Our team is composed of talented analog and digital designers from diverse backgrounds, working collaboratively to push the boundaries of technology We leverage a full suite of IC design tools, supplemented by custom, in-house tools supported by an experienced software/CAD team, to create industry-leading SerDes IP, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

Review SerDes standards to develop analog sub-block specifications. Identify and refine circuit architectures to achieve optimal power, area, and performance targets. Propose design and verification strategies that efficiently use simulator features to ensure the highest quality design. Oversee physical layout to minimize the effect of parasitics, device stress, and process variation. Present simulation data for peer and customer review. Document design features and test plans. Consult on the electrical characterization of your circuit within the SerDes IP product. Propose solutions for post-silicon design updates. The Impact You Will Have:Drive innovation in high-speed analog integrated circuit design. Ensure optimal performance, power efficiency, and area utilization of our products. Contribute to the development of industry-leading SerDes IP. Enhance the reliability and quality of our analog sub-blocks. Support the successful integration of SerDes IP into customer products. Foster collaboration and knowledge sharing within the R&D team. Influence design strategies and best practices within the organization. What You ll Need:BE with 8+ years of relevant experience or MTech with 6+ years of relevant experience in Electrical Engineering or Computer Engineering. In-depth familiarity with transistor-level circuit design and sound CMOS design fundamentals. Detailed design experience with at least one, and familiarity with several other SerDes sub-circuits. Awareness of ESD issues and circuit techniques for addressing them. Familiarity with custom digital design and high-speed logic paths. Knowledge of design for reliability, including EM, IR, and aging considerations. Experience with tools for schematic entry, physical layout, and design verification. Hands-on experience with physical layout of high-speed circuits is a plus. Proficiency with SPICE simulators and simulation methods. Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control / data-capture. Experience with scripting languages such as TCL, Perl, C, Python, or MATLAB is desired. Who You Are:Collaborative and able to work effectively in a team environment. Detail-oriented with a strong focus on quality and reliability. Proactive problem-solver with innovative design strategies. Excellent communicator with strong documentation skills. Adaptable and able to thrive in a fast-paced, dynamic environment.

Review SerDes standards to develop analog sub-block specifications. Identify and refine circuit architectures to achieve optimal power, area, and performance targets. Propose design and verification strategies that efficiently use simulator features to ensure the highest quality design. Oversee physical layout to minimize the effect of parasitics, device stress, and process variation. Present simulation data for peer and customer review. Document design features and test plans. Consult on the electrical characterization of your circuit within the SerDes IP product. Propose solutions for post-silicon design updates. The Impact You Will Have:Drive innovation in high-speed analog integrated circuit design. Ensure optimal performance, power efficiency, and area utilization of our products. Contribute to the development of industry-leading SerDes IP. Enhance the reliability and quality of our analog sub-blocks. Support the successful integration of SerDes IP into customer products. Foster collaboration and knowledge sharing within the R&D team. Influence design strategies and best practices within the organization. What You ll Need:BE with 8+ years of relevant experience or MTech with 6+ years of relevant experience in Electrical Engineering or Computer Engineering. In-depth familiarity with transistor-level circuit design and sound CMOS design fundamentals. Detailed design experience with at least one, and familiarity with several other SerDes sub-circuits. Awareness of ESD issues and circuit techniques for addressing them. Familiarity with custom digital design and high-speed logic paths. Knowledge of design for reliability, including EM, IR, and aging considerations. Experience with tools for schematic entry, physical layout, and design verification. Hands-on experience with physical layout of high-speed circuits is a plus. Proficiency with SPICE simulators and simulation methods. Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control / data-capture. Experience with scripting languages such as TCL, Perl, C, Python, or MATLAB is desired. Who You Are:Collaborative and able to work effectively in a team environment. Detail-oriented with a strong focus on quality and reliability. Proactive problem-solver with innovative design strategies. Excellent communicator with strong documentation skills. Adaptable and able to thrive in a fast-paced, dynamic environment