Senior CAD Engineer

As a Senior Formal Equivalence Checking and Synthesis Methodology Engineer at NVIDIA, you will be part of the ASIC-PD Methodology team in Bengaluru, focusing on developing, maintaining, and optimizing RTL synthesis and logic-equivalence methodologies for VLSI designs. Your role will involve creating and enhancing product design methodologies, particularly in logic-equivalence checking and RTL-synthesis, with a strong emphasis on optimization and automation. **Key Responsibilities:** - Develop and maintain equivalence checking flows (FEC/FEV) for different stages of the VLSI design cycle. - Enhance RTL Physical-Synthesis workflows at both full-chip and block-level. - Collaborate with implementation teams to understand requirements and pain-points, and enhance methodologies accordingly. - Deploy methodologies based on technology updates, design needs, and tool features. - Fine-tune design recipes for aggressive PPA targets while ensuring logical equivalence. - Optimize flows for performance, capacity, and debug capabilities. - Investigate and resolve equivalence checking issues, including setup problems and performance bottlenecks. - Develop custom scripts in tcl/perl/python for the automation of post-processing tasks. **Qualifications Required:** - B.Tech/BS in VLSI/Electronics/Electrical Engineering or Computer Science with 5+ years of ASIC design or CAD experience. - Proficiency in Verilog, ASIC design flow, and commercial EDA tools. - Strong scripting skills in Perl, Python, and TCL. - Excellent problem-solving, debugging, and analytical abilities. - Ability to work collaboratively in a team environment with multi-functional teams. - Strong communication and documentation skills. NVIDIA, known for its groundbreaking technologies, invites creative and autonomous individuals to join their diverse team in Bengaluru and contribute to making a lasting impact on the world.,