Senior Analog Layout Design Engineers / Leads

Greetings from Eximietas Design! We are currently seeking Senior Analog Layout Design Engineers/Leads with 7-15 years of experience, particularly with expertise in lower FINFET technology nodes such as TSMC 5nm/7nm. This is an exciting opportunity to join our expanding team in Visakhapatnam (Vizag) with a preferred notice period of 30 days or less. As a Senior Analog Layout Design Engineer/Lead, you will be responsible for contributing to cutting-edge analog layout design. Your key responsibilities will include optimizing IR drop, Electromigration, self-heating, RC delay, and parasitic capacitance. You should have a solid understanding of how layout impacts circuit performance, the ability to meet tight design constraints, and deliver high-quality layouts. The ideal candidate will have hands-on experience with CADENCE/SYNOPSYS layout tools and flows. Familiarity with scripting languages such as PERL/SKILL is a plus. Additionally, strong communication skills and experience collaborating with cross-functional teams are essential for success in this role. If you are interested in this opportunity or know someone who would be a great fit, please send your updated resume to maruthiprasad.e@eximietas.design. Referrals are highly appreciated. We are excited to connect with talented engineers who are passionate about pushing the boundaries of analog layout design. We look forward to hearing from you! Maruthhi Naidu Talent Associate - VLSI Manager Eximietas Design - Visakhapatnam maruthiprasad.e@eximietas.design +91 8088969910.,