Job
Description
Senior AMS Layout Engineer with 8+ years of experience , specifically with FinFET and high-speed layout expertise , based in Noida About the Role We are seeking a highly skilled and experienced Senior AMS Layout Engineer to join our advanced silicon design team in Noida . This role involves the physical layout design of analog and mixed-signal circuits , with a focus on FinFET nodes and high-speed, high-performance designs for next-generation semiconductor products. As a senior member of the team, you will work closely with circuit designers, layout leads, and verification engineers to deliver high-quality, tape-out-ready layout that meets stringent performance, power, and area (PPA) goals. Key Responsibilities Ownership of layout implementation for analog, mixed-signal, and high-speed blocks such as PLLs, LDOs, SerDes, ADCs, and high-speed I/Os. Perform layout floorplanning , transistor-level layout, and block-level integration at advanced nodes (FinFET: 7nm, 5nm, 3nm preferred). Ensure DRC, LVS, ERC, and EMIR clean layout using industry-standard tools (Cadence Virtuoso, Assura, Calibre). Collaborate with circuit design teams to understand and implement layout constraints and critical matching, shielding, symmetry, and routing rules. Execute layout optimization for performance, area, and manufacturability. Guide and review work of junior layout engineers and assist in resolving technical challenges. Work closely with physical verification and post-layout simulation teams for signoff closure. Support tape-out and post-silicon debug, as required. Required Qualifications & Skills Bachelor's or Master's degree in Electronics , Electrical Engineering , or related fields. 8+ years of proven experience in analog and mixed-signal layout design . Strong hands-on expertise in FinFET layout (e.g., 7nm and below), including handling of high-speed analog and custom digital layouts. Proficiency with Cadence Virtuoso , Assura , Calibre , and physical verification tools. Solid understanding of layout-dependent effects (LDE) , parasitic-aware layout, electromigration, and IR drop considerations. Familiarity with high-speed design constraints such as matched routing, shielding, isolation, and power planning. Excellent team collaboration and communication skills. Interested? Apply or or know someone great? Reach out via DM or WhatsApp +91 9966034636 / Send your profile to ranjith.allam@cyient.com
