36 Rtl Development Jobs

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ THE ROLE: This role will be part of Silicon Applications and Documentation engineering team in AECG. You will be working with a collaborative team focused on enabling customers to succeed when using ACAP/FPGA. You will have the opportunity to focus on Complex IPs and memory interfaces on the ACAP/FPGA platforms for specialty applications such as image sensors, IOT, emulation etc... In this cross-functional position you will interface directly with Design and Software engineering groups, and you will be the primary interface between the engineering teams and escalated customer support issues. THE PERSON: You are a team player who has excellent communication and writing skills. You have experience communicating effectively and working optimally with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are interested in debugging customer issues and leading complex projects. KEY RESPONSIBILITIES: As a member of this team, you will be responsible for the following: Creating customer documentation (datasheets, architecture manuals, product guides, errata, tutorials) Validating and characterizing memory/IO interfaces and other FPGA key features Building custom designs using Verilog, SystemVerilog or VHDL Resolving escalated customer support issues PREFERRED EXPERIENCE: Excellent written and verbal communication skills. Effective project planning and execution FPGA or ASIC design background Strong background in memory interfaces Experience in Silicon Bring-up and Hardware debug Strong background in RTL development and verification Familiarity with programming/scripting language ACADEMIC CREDENTIALS: Bachelors or Masters degree in Computer Engineering/Electrical Engineering #LI-MK1 Benefits offered are described: . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

Job Area :Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Responsibilities Front-End implementation of MSIP (Temp/Voltage/Security Sensors, Controllers) designs RTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules. Work with functional verification team on test-plan development and debug. Develop timing constraints, deliver synthesized netlist to physical design team, and provide constraints support for PD STA. UPF writing, power aware equivalence checks and low power checks. DFT insertion and ATPG analysis for optimal SAF, TDF coverage. Provide support to SoC integration and chip level pre/post-silicon debug. Skills & Experience MTech/BTech in EE/CS with hardware engineering experience of 3+ years. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.),synthesis/DFT/FV/STA. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globeand possess good communication skills.

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Responsibilities Front-End implementation of SERDES high speed Interface PHY designs RTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules. Work with functional verification team on test-plan development and debug. Develop timing constraints, deliver synthesized netlist to physical design team, and provide constraints support for PD STA. UPF writing, power aware equivalence checks and low power checks. DFT insertion and ATPG analysis for optimal SAF, TDF coverage. Provide support to SoC integration and chip level pre/post-silicon debug. Skills & Experience MTech/BTech in EE/CS with hardware engineering experience of 8+ years. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.),synthesis/DFT/FV/STA. Experience with high-speed interface design and good understanding of Industry standard protocols like USB/PCIe/MIPI, etc. is desirable. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globeand possess good communication skills.

Qualcomm India Private Limited is a leading technology innovator that strives to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, your role will involve planning, designing, optimizing, verifying, and testing electronic systems including circuits, mechanical systems, Digital/Analog/RF/optical systems, and more to launch cutting-edge products. Collaborating with cross-functional teams, you will develop solutions to meet performance requirements. To qualify for this role, you should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with at least 4 years of Hardware Engineering experience, or a Master's degree with 3+ years of experience, or a PhD with 2+ years of experience. Some of your responsibilities will include implementing SERDES high-speed Interface PHY designs, RTL development and validation, test-plan development, timing constraints development, DFT insertion, and post-silicon debug support. As a Hardware Engineer at Qualcomm, you are expected to have an MTech/BTech in EE/CS with 8+ years of hardware engineering experience. Your skillset should include micro-architecture development, RTL design, front-end flows, synthesis, DFT, STA, and experience with high-speed interface design and standard protocols like USB/PCIe/MIPI. Post-silicon bring-up and debug experience is considered a plus, along with the ability to collaborate with global teams and possess strong communication skills. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, you can reach out to disability-accommodations@qualcomm.com for support. The company expects its employees to adhere to all applicable policies and procedures, especially regarding the protection of confidential information. Please note that Qualcomm's Careers Site is intended for individuals seeking job opportunities directly with Qualcomm. Staffing and recruiting agencies or individuals represented by an agency are not authorized to use the site for submissions. Unsolicited resumes or applications from agencies will not be accepted. For more information about this role, you can contact Qualcomm Careers.,

The ideal candidate for this role should possess a strong understanding of RTL design and microarchitecture of IPs, with the ability to integrate them into sub-systems and SoCs. Responsibilities include defining the Uarch of SoC IPs, conducting RTL development, and ensuring the quality of RTL through checks such as Clock Domain Crossing (CDC) check, Lint, Design for Testability (DFT), and Low Power Checks. Additionally, the candidate will be involved in RTL synthesis, STA support, and provide pre and post-silicon functional verification support. Collaboration with different domain teams is essential for successful execution of tasks, along with a solid understanding of DDR knowledge. The candidate should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field, coupled with 6-10 years of experience in IP/SoC Design. Proficiency in SoC design and integration for complex SoCs is a prerequisite, while experience in Synthesis and understanding of timing concepts is considered advantageous. Candidates are expected to have knowledge of AMBA protocols such as AXI, AHB, and APB, in addition to expertise in SoC clocking/reset architecture. Strong RTL design and coding skills in Verilog, System Verilog, VHDL, etc., are required, along with experience in micro-architecture and design of digital IPs and subsystems.,

We are seeking an experienced Sr Go Engineer focused on Code Reasoning & Benchmarking The role involves designing algorithmically rich coding problems, building evaluation systems, and developing comprehensive benchmarks that test reasoning, correctness, and performance, This is a highly technical position requiring deep expertise in algorithms, system-level problem solving, and software engineering The ideal candidate will be a creative problem designer and a detail-oriented engineer who can deliver production-ready artifacts within a short timeframe, Key Responsibilities Problem & System Design: Create algorithmically challenging coding problems that evaluate reasoning, correctness, and efficiency in real-world software scenarios, Robust Development: Write clean, modular, and production-quality Java code along with comprehensive test suites covering correctness, edge cases, and performance, Technical Specifications: Draft clear, precise, and unambiguous specifications and problem statements with well-defined constraints and evaluation criteria, Algorithm Coverage: Ensure strong representation across multiple domains including data structures, graph algorithms, number theory, performance optimization, and constraint-based design, Metadata & Documentation: Apply structured metadata to all problems including taxonomy, difficulty levels, and domain relevance to maintain consistency and reproducibility, Quality Assurance: Participate in peer reviews and validation cycles to maintain high engineering and system integrity standards, Deliverables: Provide well-documented, maintainable, and scalable outputs ready for integration into production environments or downstream applications, Requirements Experience: 5+ years in software engineering, algorithm design, or systems-level programming, Language Proficiency: Strong command of Go (4+ years) with ability to implement high-performance solutions, Algorithmic Strength: Solid understanding of complexity analysis, optimization, and computational constraints, Test Engineering: Hands-on experience with test automation, benchmarks, or large-scale evaluation systems, Tooling Knowledge: Familiarity with version control (e-g , Git) and structured data formats (JSON, YAML), Domain Expertise Candidates should demonstrate fluency in at least four of the following areas: Core Data Structures: Trie, Segment Tree, Union-Find Algorithmic Paradigms: Dynamic Programming, Greedy Algorithms, Bitmasking Graph Algorithms: Shortest Paths, Network Flow, Topological Sorting Mathematics & Number Theory: Geometry, Probability, Modular Arithmetic String Processing: Suffix Trees, Rolling Hashing, Pattern Matching Advanced Topics: 2-SAT, FFT, Linear Programming

Qualcomm India Private Limited is seeking an experienced RTL designer to join the DSP processor team. In this role, you will be responsible for developing RTL for multiple logic blocks of a DSP core. You will work closely with various teams including physical design, power optimization, and verification to ensure successful project completion. The ideal candidate will have 10 to 15 years of practical experience in RTL development using VHDL and/or Verilog. You should have a strong understanding of functional and structural RTL design, design partitioning, simulation, and collaboration with the design verification team. Familiarity with the latest RTL languages and tools such as Modelsim, VCS, Design Compile, Prime Time, Linting tools, CDC tools, UPF, and System Verilog Assertion is essential. Experience in processor architecture, microarchitecture implementation, microprocessor integration, and low power design is highly desirable for this role. You will also be responsible for running various frontend tools to check for linting, clock domain crossing, and synthesis, as well as working on design constraints and timing closure with the physical design team. To qualify for this position, you must have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering experience, or a Master's degree with 5+ years of experience, or a PhD with 4+ years of experience. Qualcomm is an equal opportunity employer and is committed to providing reasonable accommodations for individuals with disabilities during the application/hiring process. If you have a disability and require assistance, please contact Qualcomm at disability-accommodations@qualcomm.com or through their toll-free number. If you are passionate about RTL design and are looking to join a dynamic team at Qualcomm, we encourage you to apply for this exciting opportunity.,

Work Location : Bangalore /Noida. Position : Software Architect. Job Description: We are seeking a skilled HW Design architect (director grade) to lead building representative SoC designs using partner systems and Cadence IP collateral. The main objective is to put together large RTL SoC Designs with high degree of configurability. Experience with SoC design, verification and performance analysis is desired. Skills needed: 15+ years of hands-on RTL Integration/development experience & hands-on verification experience Knowledge and experience in Verilog/System Verilog and UVM Experience with performance analysis of complex hardware-software systems. Well versed in object-oriented design, System-C/C/C++ programming experience is a plus Familiarity with standard communication protocols Emulation experience on Palladium/Protium would be a plus Past background in tool development is a plus Behavioral skills required: Must possess strong written, verbal and presentation skills. Good communication and interpersonal skills, demonstrate teamwork and collaboration skills. Explore whats possible to get the job done, including creative use of unconventional solutions Work effectively across functions and geographies Push to raise the bar while always operating with integrity

As an experienced professional in Electrical Engineering or Electronics and Communication, you will be responsible for defining and driving System-on-Chip (SoC) Architecture while conducting thorough Power, Performance, and Area (PPA) trade-off analysis. Your role will involve leading the selection and integration strategies of IPs for performance-driven designs. Additionally, you will be tasked with architecting and reviewing Mixed Signal Designs and Multi-core Processor Subsystems. Collaboration is key in this role as you will work closely with RTL to Physical Design teams to ensure high-quality deliverables and coordinate with Physical Design (PD) teams for successful Tapeout activities. It will be your responsibility to ensure that the architectural decisions align with foundry node requirements across various technology nodes such as 28nm, 16nm, 7nm, and others. To excel in this position, you should have a minimum of 18 years of experience post Engineering degree, with a demonstrated track record in SoC design methodologies and architecture definition. A deep understanding of RTL development, integration, and backend handoff is essential. Your cross-functional collaboration skills will be put to the test as you engage with analog, PD, DFT, and software teams. Exposure to foundry-specific constraints and best practices across different technology nodes will be an advantage. If you are looking for a challenging yet rewarding opportunity to contribute your expertise in SoC architecture and design methodologies, this role offers a platform for you to showcase your skills and make a significant impact in the semiconductor industry.,

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology-and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. We are now looking for RTL Design engineers for our BOOT and Power management Subsystem Design deployed in Automotive and Client chips. As one of the primary designers, you will be responsible for implementing system BOOT and overall power management architecture of next generation chips. One should possess strong digital design and verification fundamentals. What you'll be doing: As a senior designer, be responsible for making architectural trade-offs based on feature/performance/power requirements, analyze system implications, come up with the micro-architecture, implement RTL, drive the verification, close timing, and support silicon validation. During the course of a project you would end up driving the following aspects of design for your unit: Own micro-architecture and RTL development of design modules Micro-architect features to meet performance, power and area requirements Work with HW architects to define critical features Work with verification teams to verify the correctness of implemented features Partner with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable. What we need to see: BTech/MTech with 3+ years of experience in crafting complex Units and CPU/micro-controller based Sub-systems Knowledge of security standards, protocols and system security architectures of modern SOC's would be a significant plus Excellent influencing skills resulting in collaboration with cross-cultural, multi geography and matrixed teams Good debugging, analytical and problem solving skills Great interpersonal skills and ability to work as an excellent teammate We have some of the most brilliant and talented people in the world working for us. If you're creative and independent, with a genuine real passion for technology and improving the state of art, we want to hear from you! Widely considered to be one of the technology world's most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law. #LI-Hybrid

Responsibilities: * Develop RTL designs using Verilog/SystemVerilog * Ensure compliance with MISC industry standards * Collaborate on microarchitecture design projects

What You'll Do Cisco SiliconOne team is looking for an expert and talented ASIC Engineer. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products. Responsibilities Looking for a Front-end Design ASIC Engineer. Architectural work: in-depth understanding of the architecture, and identification of problems and solutions. All aspects of implementation: specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for low power and area; highlighting issues and standard methodologies for power and area optimization. Document and improve standard methodologies to make product successful. Who You Are Worked in architecture and definition of high-scale, high-performance ASICs. Validated experience in implementation: specification, RTL design, lint, cdc, timing analysis, formal verification, system testing. Validated experience in flow automation (scripting, Makefiles, etc), and establishing guidelines for the team. Good interpersonal skills, and validated leadership to accurately describe issues/improvements and lead team for on-time completion. BS/MS and 5+/3+ years respectively of hands-on experience in large-scale, high-performance ASIC BS/MS should be in EE/CS. Minimum Qualifications RTL development (Verilog, SystemVerilog, VCS, Spyglass, CDC, Formal verification) Experienced in system debug and SW/HW bringup, system validation of silicon towards FCS. Gate-level understanding of RTL and Synthesis Programming/scripting skills (C, C++, Perl) Hardware Emulation Platforms and tools (such as EVE, Veloce) Good written/verbal interpersonal skills and leadership skills. Who You'll Work With Come join us and be part of the Cisco SiliconOne team and take part in crafting Cisco's groundbreaking Enterprise and Service Provider solutions by crafting some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry, security, etc). Our group offers a rare combination of a startup culture with the benefits of working for the top tier networking company in the world!

General Summary Qualcomm is a leading technology innovator, pushing the boundaries of what's possible to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, you will: Plan, design, optimize, verify, and test electronic systems. Work on yield bring-up, circuits, mechanical systems, digital/analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Collaborate with cross-functional teams to develop solutions and meet performance requirements. Contribute to launching cutting-edge, world-class products. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with 2+ years of relevant hardware engineering experience, OR Master's degree in the above fields with 1+ year of relevant experience, OR PhD in the above fields. Additional minimum qualifications include: Bachelor's degree in Science, Engineering, or closely related field. Experience with digital design and RTL development. Experience using front-end EDA tools such as Synopsys Next Generation tools, Conformal LEC, Synopsys Formality, and Synopsys PrimeTime. Preferred Qualifications Knowledge and experience in graphics design and development. Proficiency in scripting languages such as Perl, TCL, and shell scripting. Strong interpersonal and teamwork skills with the ability to work independently. Ability to solve complex, unique, and detailed technical problems. Familiarity with the latest EDA tools for synthesis, formal verification, timing analysis, and physical design.

What You'll Do Cisco SiliconOne team is looking for an expert and talented ASIC Engineer. You will have an ASIC design background with hands-on experience in RTL design with in-depth knowledge of ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products. Responsibilities Looking for a Front-end Design ASIC Engineer. Architectural work: in-depth understanding of the architecture, and identification of problems and solutions. All aspects of implementation: specification, design, timing-analysis, power-optimization, flow automation, optimization of the logic for low power and area; highlighting issues and standard methodologies for power and area optimization. Document and improve standard methodologies to make product successful. Who You Are Worked in architecture and definition of high-scale, high-performance ASICs. Validated experience in implementation: specification, RTL design, lint, cdc, timing analysis, formal verification, system testing. Validated experience in flow automation (scripting, Makefiles, etc), and establishing guidelines for the team. Good interpersonal skills, and validated leadership to accurately describe issues/improvements and lead team for on-time completion. BS/MS and 8+/6+ years respectively of hands-on experience in large-scale, high-performance ASIC BS/MS should be in EE/CS. Minimum Qualifications RTL development (Verilog, SystemVerilog, VCS, Spyglass, CDC, Formal verification) Experienced in system debug and SW/HW bringup, system validation of silicon towards FCS. Gate-level understanding of RTL and Synthesis Programming/scripting skills (C, C++, Perl) Hardware Emulation Platforms and tools (such as EVE, Veloce) Good written/verbal interpersonal skills and leadership skills.

We are looking for an experienced Staff Design Engineer CPU RTL to take on the responsibility of leading and owning RTL development for one or more modules of a high-performance CPU core. Your role will encompass all facets of the design, including Performance, Power, and Area. In this position, you will be expected to drive the micro-architecture and design of a critical CPU block or multiple blocks of a CPU core. You will work closely with the CPU modeling team to explore high-performance strategies. Your responsibilities will also include developing microarchitecture and specifications, configuring design features, and refining RTL design to meet power, performance, area, and timing objectives. Additionally, you will provide support for functional verification and assist in defining the design verification strategy. Collaborating with a multi-functional engineering team, you will help implement and validate physical design aspects related to timing, area, reliability, testability, and power. To qualify for this role, you must have hands-on working knowledge of the pipeline stages of an in-order or out-of-order high-performance CPU core. A thorough understanding of microprocessor architecture is essential, particularly in areas such as Instruction fetch and decode, branch prediction, Instruction scheduling, register renaming, Out-of-order execution, Integer and Floating-point execution, Load, Store execution, prefetching, Cache, and memory subsystems. Proficiency in Verilog and/or VHDL, experience with simulators and waveform debugging tools, and knowledge of logic design principles are required. Ideally, you should hold a Masters degree with 5-8 years of experience or a PhD with 3-4 years of work experience. Candidates with experience in designing RISC-V, ARM, and/or MIPS CPUs, hardware multi-threading, virtualization, and SIMD designs will be given bonus points. Familiarity with high-performance and low-power microarchitecture techniques, as well as expertise in using scripting languages like Perl or Python, is advantageous. At MIPS, you will be joining a dynamic team of technologists dedicated to developing the industry's highest performance RISC-V processors. You will have the opportunity to work in small teams within a non-compartmentalized structure, offering autonomy and the chance to contribute to the bigger picture. With support from experienced CPU engineers, you can chart your own growth path within the organization. Additionally, you will gain valuable insights into the RISC-V architecture and its applications by working with industry-leading customers. MIPS offers a competitive benefits package that includes medical, dental, vision, retirement savings, and paid leave for employees and their families. MIPS is recognized as a pioneer in microprocessor technology, with a legacy of leading RISC-based computing for various applications. Building on over 30 years of expertise, MIPS is at the forefront of the RISC-V revolution, focusing on developing high-performance processors like the MIPS eVocore series. As a part of the MIPS team, you will play a key role in accelerating the adoption of RISC-V solutions with cutting-edge technologies and deep engineering knowledge.,

NVIDIA is at the forefront of innovation, continually reinventing itself to tackle the challenges of the modern world. The invention of the GPU by NVIDIA has not only driven the growth of the PC gaming market but has also redefined computer graphics and revolutionized parallel computing. In today's era of booming artificial intelligence research, there is a crucial need for highly scalable and massively parallel computation power, an area where NVIDIA GPUs excel. At NVIDIA, we are committed to amplifying human creativity and intelligence through our constant evolution and adaptation to new opportunities that are uniquely challenging and impactful. As part of our team, you will be immersed in a diverse and supportive environment that encourages everyone to strive for excellence and make a significant impact on the world. Currently, we are seeking motivated and innovative ASIC / Hardware Engineers to join us in architecting, designing, and verifying the next generation of GPUs, CPUs, and SoCs. These cutting-edge technologies are aimed at accelerating the performance of various applications such as Data Center, Machine Learning, Autonomous Driving, Ray Tracing, and more. As a part of our hardware engineering groups, you will work on high-performance GPU/SOC/CPU projects involving Memory subsystems, Graphic Processing Units, NOC-based Interconnect Fabric, High-speed IOs, and more. Your responsibilities will include: - Working on hardware models at different levels of abstraction to identify performance bottlenecks. - Collaborating with architecture and design teams to analyze architecture trade-offs related to performance, area, and power consumption. - Developing and testing workloads and test suites targeting different applications running on our products. - Making architectural trade-offs based on various requirements and driving the verification and validation processes. - Creating verification environments using UVM methodology and driving functional coverage verification closure. - Enhancing timing analysis workflows and assisting in chip-level integration and floor planning. - Designing state-of-the-art test access mechanisms and DFT methodologies for our products. - Collaborating with cross-functional teams to drive innovation and improve DFT methods. To be successful in this role, you should have: - A BTech/MTech degree with at least 2 years of experience in micro-architecture and RTL development. - Strong digital design fundamentals and familiarity with ASIC design flows. - Experience in GPU/CPU/SOC performance verification and analysis, IP/SOC design, micro-architecture, and other relevant skills. - Excellent debugging, analytical, and interpersonal skills, along with the ability to work effectively in a team. If you are passionate about technology and seeking a challenging yet rewarding opportunity, NVIDIA offers competitive salaries, comprehensive benefits, and a stimulating work environment with some of the brightest minds in the industry. Join us in our mission to shape the future of technology and make a meaningful contribution to the world.,

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Synthesis, LEC, Low power checks, Memory BIST insertion, Constraints validation. Development of signoff quality constraints and the development of power intent constraints. May also include running RTL Lint, CLP, MEMBIST, DFT DRC etc. TCL script development in addition to running/analyzing/debugging designs. Hands on with Synopsys DCG/Genus/Fusion Compiler. Hands on with Synopsys Prime Time including constraint development for complex blocks with multiple clock domains. Hands on with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development Experience with either RTL development or Physical Design is also a plus 6+ years experience Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

As a Silicon Design Engineer with over 5 years of experience in RTL design and development, you will be responsible for creating RTL designs and developing various documents such as requirements specification, design, user guides, etc. Your expertise in FPGA VHDL and/or Verilog design using Xilinx technology and tools will be crucial in this role. Additionally, your experience with Ethernet, PCIe, SPI, I2C, USB, GPIO, Memory architectures, DDR, SDRAM, DMA technologies, and hardware testing will be valuable assets. You should be adept at HW testing, including working with test equipment such as logic and traffic analyzers, test generators, etc. Strong debugging skills at both device and board levels will be essential. Proficiency in scripting languages like Perl, Python, or TCL will be beneficial. Your excellent interpersonal, written, and verbal communication skills will enable you to collaborate effectively with cross-functional teams. Moreover, your problem-solving and analytical skills will be put to good use in this dynamic role. If you are interested in this opportunity, please submit your updated resume to janagaradha.n@acldigital.com. Your contributions as a Silicon Design Engineer will play a vital role in the successful development of cutting-edge technology solutions.,

Qualcomm India Private Limited is a leading technology innovator that is dedicated to pushing the boundaries of what is possible. As a Qualcomm Hardware Engineer, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems. These systems encompass a wide range of components such as yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Your work will contribute to the development of cutting-edge, world-class products that drive digital transformation and enable next-generation experiences. To qualify for this role, you must hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field, along with at least 3 years of Hardware Engineering or related work experience. Alternatively, a Master's degree with 2+ years of experience or a PhD with 1+ year of experience in the relevant field will also be considered. As a Hardware Engineer at Qualcomm, your responsibilities will include front-end implementation of SERDES high-speed Interface PHY designs, RTL development and validation, collaboration with the functional verification team, development of timing constraints, UPF writing, DFT insertion, ATPG analysis, and support for SoC integration and chip level pre/post-silicon debug. The ideal candidate for this role should possess an MTech/BTech in EE/CS with 4 to 7 years of hardware engineering experience. You should have expertise in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA, high-speed interface design, and industry-standard protocols like USB/PCIe/MIPI. Experience with post-silicon bring-up and debug is considered a plus, along with the ability to collaborate effectively with global teams and excellent communication skills. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, you can reach out to disability-accommodations@qualcomm.com or Qualcomm's toll-free number. The company expects its employees to adhere to all applicable policies and procedures, including those related to the protection of confidential information. Please note that Qualcomm's Careers Site is intended for individuals seeking jobs directly at Qualcomm. Staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes through the site. Unsolicited submissions from agencies will not be accepted, and Qualcomm does not entertain any fees related to such submissions. For further information about this role, you can contact Qualcomm Careers for assistance.,

Qualcomm India Private Limited is seeking a Hardware Engineer to be a part of the Engineering Group, specifically in the Hardware Engineering team. As a Qualcomm Hardware Engineer, you will be involved in various aspects of planning, designing, optimizing, verifying, and testing electronic systems. This role will require you to work on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to contribute to the development of cutting-edge, world-class products. Collaboration with cross-functional teams is essential to develop solutions that meet performance requirements. To be considered for this position, you must have a minimum of a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field, along with at least 3 years of Hardware Engineering or related work experience. Alternatively, a Master's degree with 2+ years of experience or a PhD with 1+ year of experience in the same fields will also be considered. Proficiency in Synthesis, LEC, Low power checks, Memory BIST insertion, Constraints validation, and the development of signoff quality constraints and power intent constraints is required. Experience with TCL script development, RTL development, or Physical Design will be advantageous. The ideal candidate should have at least 6 years of experience in Hardware Engineering. Qualcomm is an equal opportunity employer and is committed to providing reasonable accommodations for individuals with disabilities during the application/hiring process. If you require an accommodation, please contact disability-accommodations@qualcomm.com. Qualcomm expects its employees to adhere to all applicable policies and procedures, including those related to the protection of company confidential information. Please note that Qualcomm's Careers Site is intended for individuals seeking job opportunities directly with Qualcomm. Staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes through the Careers Site. Unsolicited submissions from agencies will not be accepted. For more information about this role, please reach out to Qualcomm Careers directly.,

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Responsibilities Front-End implementation of MSIP (Temp/Voltage/Security Sensors, Controllers) designs RTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules. Work with functional verification team on test-plan development and debug. Develop timing constraints, deliver synthesized netlist to physical design team, and provide constraints support for PD STA. UPF writing, power aware equivalence checks and low power checks. DFT insertion and ATPG analysis for optimal SAF, TDF coverage. Provide support to SoC integration and chip level pre/post-silicon debug. Skills & Experience MTech/BTech in EE/CS with hardware engineering experience of 5+ years. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globe and possess good communication skills. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Development of Specifications, Micro Architecture, RTL Development for Digital IPs. Setup and use standard EDA tools for Verification, Lint CDC, Synthesis, Power Analysis tools for Verification and Ensuring PPA for IP developed. Conduct Reviews for Documentation, RTL and Verification Tests. Experience and Skills Required 5 to 15 years of experience in SoC/IP Design. Expertise in Writing Detailed IP Specifications, Micro Architecture, IP design, Subsystem and SoC level integration. Expertise on RTL Development. Follow Coding Standards, expertise on Lint, CDC tools, verification and debugging of test cases, code and functional coverage analysis. In-depth knowledge of Clocking Methodology, Low Power Implementation. Hands on experience on writing constraints and exceptions, performing Synthesis, Timing Analysis and Design for Test Implementation. Experience of power partitioning and usage of CPF/UPF. Exposure to IP Design for ARM Microcontrollers based SoCs. Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB). Knowledge of one or more of the interface protocols, PCIe, DDR, Ethernet, I2C, UART, SPI. Experience in Matlab Simulations and Implementing Signal Processing IPs like Digital Filters, Math Functions or FFT engines. Experience in developing Security IPs for various Encryption standards. Experience in implementing On-chip Memory and Flash controllers. Soft Skills Strong analytical, problem-solving, and hands-on skills. Self-driven and thrives when facing open-ended tasks. Start-up mentality: fast-paced, flexible and team-oriented. Good written and verbal communication skills with great documentation skills. Flexibility to work with varied schedules and tolerance for ambiguity.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Responsibilities Front-End implementation of SERDES high speed Interface PHY designs RTL development and its validation for linting, clock-domain crossing, conformal low power and DFT rules. Work with functional verification team on test-plan development and debug. Develop timing constraints, deliver synthesized netlist to physical design team, and provide constraints support for PD STA. UPF writing, power aware equivalence checks and low power checks. DFT insertion and ATPG analysis for optimal SAF, TDF coverage. Provide support to SoC integration and chip level pre/post-silicon debug. Skills & Experience MTech/BTech in EE/CS with hardware engineering experience of 4 to 7 years. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA. Experience with high-speed interface design and good understanding of Industry standard protocols like USB/PCIe/MIPI, etc. is desirable. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globe and possess good communication skills.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Looking for a highly talented and a technically strong leader with an eye for quality to lead a high performing and talented team of engineers in the implementation domain for Display Sub-System. Able to handle multiple project execution that are time critical and complex Able to communicate effectively with all stakeholders across the organization Able to collaborate with cross functional teams for upholding the best practices and enabling smooth execution Focus on improving execution efficiency and improve on the optimizations in area, power and performance. Able to grow the team in terms of technical depth and size as we do more and more projects Able to innovate and bring fresh ideas Bachelor’s or master’s degree in engineering with 9-13+ Years of experience. Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools. Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure. Experience in all aspects of timing closure for multi-clock domain designs. Should be familiar with MCMM synthesis and optimization. Should have good understanding of low-power design implementation using UPF. Experience with scripting language such as Perl/ Python, TCL. Experience with different power optimization flows or technique such as clock gating. Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation Should be able to handle ECOs and formal verification and maintain high quality matrix Responsibilities include Synthesis, LEC, Low power checks, Memory BIST insertion, Constraints validation. Development of signoff quality constraints and the development of power intent constraints. May also include running RTL Lint, CLP, MEMBIST, DFT DRC etc. TCL script development in addition to running/analyzing/debugging designs. Hands on with Synopsys DCG/Genus/Fusion Compiler. Hands on with Synopsys Prime Time including constraint development for complex blocks with multiple clock domains. Hands on with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development Experience with either RTL development or Physical Design is also a plus

Minimum qualifications:. Bachelor’s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience.. 15 years of experience in ASIC RTL design.. Experience with RTL design using Verilog/System Verilog and microarchitecture.. Experience with ARM-based SoCs, interconnects and ASIC methodology.. Preferred qualifications:. Master’s degree in Electrical Engineering or Computer Engineering.. Experience driving multi-generational roadmap for IP development.. Experience leading interconnect IP design team for low power SoCs.. About The Job. Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.. Responsibilities. Lead a team of people to deliver fabric interconnect design.. Develop and refine RTL design to aim power, performance, area, and timing goals.. Define details such as interface protocol, block diagram, data flow, pipelines, etc.. Oversee RTL development, debug functional/performance simulations.. Communicate and work with multi-disciplined and multi-site teams.. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .. Show more Show less