Posted:11 hours ago|
Platform:
Work from Office
Full Time
General Summary:
8 to 14 years of work experience in ASIC RTL Design Experience in Logic design/micro-architecture/RTL coding is a must. Must have hands on experience with design and integration of complex multi clock domain blocks Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, clocking/reset/debug architecture Hands on experience in Multi Clock designs, Asynchronous interface is a must. Understanding of DSP and microprocessors is an added advantage Work closely with the Design verification and validation teams for pre/post Silicon debug Hands on experience in Low power design is required Experience in Synthesis / Understanding of timing concepts for ASIC is and added advantage.
Minimum Qualifications:
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.Preferred Qualifications:
Principal Duties and Responsibilities:
Level of Responsibility:
Qualcomm
Upload Resume
Drag or click to upload
Your data is secure with us, protected by advanced encryption.
Browse through a variety of job opportunities tailored to your skills and preferences. Filter by location, experience, salary, and more to find your perfect fit.
We have sent an OTP to your contact. Please enter it below to verify.
bengaluru
12.0 - 17.0 Lacs P.A.
bengaluru
1.71302 - 7.0 Lacs P.A.
14.0 - 18.0 Lacs P.A.
16.0 - 20.0 Lacs P.A.
bengaluru
11.0 - 16.0 Lacs P.A.
bengaluru
12.0 - 17.0 Lacs P.A.
14.0 - 18.0 Lacs P.A.
bengaluru
12.0 - 17.0 Lacs P.A.
bengaluru
13.0 - 17.0 Lacs P.A.
13.0 - 17.0 Lacs P.A.