R&D Engineer, Staff (STA)

Job Description

You Are: You are an experienced and initiative-taking individual with a strong technical background in STA at IP/block/full chip level implementation/methodology. You thrive in collaborative environments and possess a passion for creating innovative technology. Your expertise lies in working with advanced Finfet and GAA process challenges, and you have a proactive analytical approach with a keen eye for detail. Your dedication to delivering high-quality results is complemented by excellent communication and people skills, allowing you to effectively collaborate with both internal teams and external customers. Driven by a desire to innovate, you are eager to contribute to the success of our cutting-edge technology products. What Youll Be Doing: * Conceptualizing, designing, and productizing state-of-the-art RTL to GDS implementation for SLM monitors realized through ASIC design flow. * Designing on-chip Process, Voltage, Temperature, glitch, and Droop monitors for monitoring silicon biometrics. * Developing Digital BE activities includes synthesis, pre-layout STA, SDC constraints development, placement, CTS, routing and collaborating with the different functional teams to achieve optimal design solutions. * Post layout STA, timing & functional ECO development, timing signoff methodology at higher frequency IP designs closure. * Co-work with Place & Route team to resolve full chip/IP/block level layout integration issues to drive timing closure. * Coordinates with internal RTL IP owners on constraints related issues. * Creating new flows/methodologies and updating existing ones through collaboration with architects, Physical design and RTL design engineering teams. * Pre-layout and post-layout timing closure and timing model characterizations across various design corners to ensure reliability and aging requirements for Automotive & consumer products. The Impact You Will Have: * Accelerating the integration of next-generation intelligent in-chip sensors and analytics into technology products. * Optimizing performance, power, area, schedule, and yield of semiconductor lifecycle stages. * Enhancing the reliability and differentiation of products in the market with reduced risk. * Driving innovation in STA and signoff design methodologies and tools. * Contributing to the development of industry-leading SLM monitors and silicon biometrics solutions. * Collaborating with cross-functional teams to ensure the successful deployment of advanced technologies. What You’ll Need: * BS/B.Tech or MS/M.Tech degree in Electrical Engineering with 5+ years of relevant industry experience. * Strong PD, pre& post layout STA and signoff experience, including SDC development, Mutli mode design development experience. *Experience in functional, test (shift, capture and at-speed ) constraints development experience and timing closure with MCMM is mandatory. * Experience in generating ECO for DRV cleaning and timing closure is mandatory. * Proficiency with Digital design tool from any EDA vendor, preferably from Synopsys tools like FC/PT/PT-PX * Sound understanding of Physical design, STA and signoff concepts. *Proven track record of successful timing closure & tape-outs in advanced nodes (14nm, 10nm, 7nm, 5nm,3nm,2nm etc...) *Good understanding of OCV, POCV, derates, crosstalk and design margins. * Experience with design methodologies like developing custom scripts and enhancing flows for better execution. Experience in scripting with TCL/PERL is required. Who You Are: * Proactive and detail-oriented with excellent problem-solving skills. * Adept at working independently and providing physical design and signoff solutions. * Excellent communicator and team player, capable of collaborating effectively with diverse teams. * Innovative thinker with a passion for technology and continuous improvement. * Committed to delivering high-quality results and achieving project goals.