Principal Power Management Circuit Engineer

As a Principal/Staff Circuit Engineer specializing in PMIC/Clock IC, your role involves leading the design and development of advanced power-management circuits and PLL IPs for complex SoCs. Your expertise in analog/mixed-signal technologies is crucial for success in this senior technical position. Key Responsibilities: - Lead the design of various power-management circuits including LDOs (ultra-low noise, capless, fast-transient), DC-DC converters (PWM/PFM), and voltage regulators. - Design and implement high-performance PLL circuits for frequency synthesis and clock generation. - Conduct advanced transistor-level simulations, modeling, and analysis to ensure performance and robustness. - Collaborate closely with layout teams to provide guidance on floorplanning, layout practices, and physical design reviews. - Oversee lab bring-up, silicon debug, and characterization of PMIC and PLL circuits. - Define specifications and system-level requirements in coordination with architecture and SoC teams. - Mentor and support junior engineers in circuit design, simulation, and lab methodologies. Qualification Required: - Bachelor's or Master's degree in Electrical Engineering or a related field. - 10+ years of hands-on experience in power-management and PLL circuit design. - Strong foundation in analog/mixed-signal fundamentals and feedback loop stability. - Expertise in designing LDOs, DC-DC converters, voltage regulators, and PLL building blocks. - Proficiency with industry-standard simulation tools such as Cadence Virtuoso, Spectre, ADE, etc. - Extensive experience with lab testing, silicon validation, and characterization equipment. In this role, your deep expertise and leadership will be instrumental in driving innovation and ensuring the successful development of cutting-edge power-management and PLL circuits for complex SoCs.,