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Infineon
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Principal Engineer / DFT

Principal Engineer / DFT

12 - 17 years

|

14 - 19 Lacs

Posted:1 day ago| Platform:

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Skills Required

asic semiconductor jtag dft analytical soc atpg perl silicon python

Work Mode

Work from Office

Job Type

Full Time

Job Description

Responsible for SoC DFT Architecture definition / implementation / verification / silicon debug of SoC/Full Chip.
Job Description

In your new role you will:

Responsible for SoC DFT Architecture definition / implementation / verification / silicon debug of SoC/Full Chip.
Need to implement Scan insertion, LPCT, LBIST, Hybrid-TK, Compression Logic and DRC analysis of implemented Testability logic structures.
Responsible for ATPG, DRC analysis, Test coverage debug, Memory BIST implementation and verification.
Owner ship of JTAG/BSCAN/iJTAG, P1500 implementation and verification, Stuck-at / TDF / Bridging / Cell-aware / iddq fault models.
Good debug skills in ZERO delay and SDF based scan/MBIST/JTAG simulations.
Hands on experience in analysis and debug of above-mentioned test domains.
Hands of experience in post silicon debug of scan/MBIST patterns/yield fall out.

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