Power Management PMIC Development Lead

Please find the below JD

Experience

Location

Notice:

Key Responsibilities

Platform PMIC Architecture & Development

• Define and architect power management solutions for SoC platforms (mobile, automotive, compute, wearable, or IoT).
• Lead development of PMIC components (buck, boost, LDOs, load switches, battery chargers, ADCs).
• Drive design reviews and architecture trade-offs (efficiency, area, thermals, sequencing, DVS).

Technical Leadership

• Lead a team of analog/mixed-signal designers, validation engineers, and layout teams.
• Collaborate with SoC power architects on vreg-mapping, power rail dependency graphs, and GDSC (Generic Dynamic Supply Controller) interactions.
• Own PMIC silicon delivery from design to validation and production handoff.
• Collaborate with SoC architects, platform teams, and power/firmware engineers on power domain definitions.

System Integration & Validation

• Ensure successful integration of PMIC with SoC platforms (power trees, sequencing, OTP, I2C/SPI control).
• Drive post-silicon bring-up of power rails using tools like QPST, QXDM, QFIL, and PMIC Debugger GUI.
• Debug and resolve power domain issues via debug UART logs, pmic logs (pm-log), and QDSS traces.
• Own system power profiling, leakage reduction, and rail characterization in coordination with Power Debug and Test (PDAT) teams.

Cross-Team Collaboration

• Work with digital designers, RTL/verification, software/firmware, DFT, layout, and packaging teams.
• PWork with board design teams to integrate PMIC reference schematics (QSCs/QRBs) into production hardware.
• Collaborate with firmware/software (LK/ABL/UEFI/Device Tree) and kernel teams to align PMIC control logic in APM, RPMh, SPM, and TZ.
• Guide layout and packaging teams on power delivery constraints, load-line, IR drop, and thermal limitations.

Required Expertise

Technical Background

• Strong knowledge of PMIC design (DC/DC converters, LDOs, bandgap references, protection circuits).
• Hands-on experience in analog/mixed-signal simulation tools (e.g., Cadence Spectre, HSPICE, Virtuoso).
• Experience with OTP, I2C/SPI/PMBus interfaces, power sequencing, dynamic voltage scaling (DVS).

Platform/System Experience

• Familiarity with SoC-level power domain design, DVFS, and board-level PMIC integration.
• Experience with power modeling, system-level power estimation, and trade-off analysis.
• Working knowledge of Linux/RTOS power management frameworks and firmware control.

Tools & Methodology

• Proficient in AMS design flows, schematic capture, layout review, verification (Verilog-A, AMS co-sim).
• Experience with lab equipment (oscilloscopes, power analyzers, electronic loads).
• Knowledge of ATE test flows, yield optimization, and characterization techniques.

Leadership Skills

• Strong technical program management and team mentoring experience.
• Ability to lead cross-functional design teams in a matrixed organization.
• Excellent documentation, communication, and stakeholder engagement skills.