PMTS Silicon Design Engineer

Job Description

PMTS SILICON DESIGN ENGINEER THE ROLE: We are seeking a seasoned SoC DFT Design Lead with expertise or significant interest in DFT Architecture. You have had significant success driving DFT Architecture, Design for DFT, Scan/ATPG with high coverage goals, with high focus on quality pattern delivery as "First Time Right". You are meticulous about Tester Time, DFT mode Power, and high performance achievement in DFT modes. THE PERSON: You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: Implement or define micro achitecture for DFT, working with functional architects and product DFT Architect, drive technical specifications and provide technical direction to execution teams Work cross with IP and Post Silicon Engineering teams, make sure to define right DFT design as First Time Right. Knowledge sharing and other contributions to ATE and Silicon Testing Teams As an overall DFT owner, responsible for post silicon debug (if any) making sure to provide right solutions for fixing the issues/provide work arounds while bringing up the silicon on Tester Work closely with Design teams for Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution and Signoff of patterns to ATE teams ACADEMIC CREDENTIALS: Bachelor s or Master s degree in related discipline preferred #LI-PK2 Benefits offered are described: AMD benefits at a glance .