15.0 - 20.0 years
15.0 - 20.0 Lacs P.A.
Hyderabad
Posted:1 week ago| Platform:
Work from Office
Full Time
PMTS SILICON DESIGN ENGINEER THE ROLE: Should have 15+ years of experience in Physical Design methodologies and Fullchip Design. You have had significant success driving Fullchip Floorplan, Fullchip Place and Route , Fullchip timing. You are meticulous about Power, Performance and Area while driving schedule and managing cost. This senior role will stretch you as you lead Physical Design teams in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design teams and business unit executives. THE PERSON: You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: Should own and drive the Physical implementation and Full chip timing closure of multiple designs of next gen 3nm (or lower nodes) SOC. Role inovolves interaction with multiple design teams, CAD teams and Tool vendors (on and cross sites) Understand and drive the requirements, define the design implementation methodology, Resource allocation, Scheduling, Resource management and Risk management etc. Ability to learn, make progress and critical times and agility is preferred. Work closely with multiple Design teams for Area , Floorplan refinement and Timing targets PREFERRED EXPERIENCE: Should have 15+ years of experience in Physical Design methodologies , Fullchip Floorplan, Fullchip Place and Route, Fullchip timing signoff closure Automation skills TCL, Perl are must Should have experience with 3nm/2nm design methodology Should have lead team of 15 members and well versed with Tracking, Goal settings and Performance evaluations Excellent communication, management, and presentation skills. Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies ACADEMIC CREDENTIALS: Bachelor s or Master s degree in related discipline preferred
Upload Resume
Drag or click to upload
Your data is secure with us, protected by advanced encryption.
Experience: Not specified
17.0 - 18.0 Lacs P.A.
Salary: Not disclosed
5.0 - 9.53 Lacs P.A.
5.0 - 9.53 Lacs P.A.
Salary: Not disclosed
Experience: Not specified
2.0 - 7.0 Lacs P.A.
15.0 - 20.0 Lacs P.A.
Experience: Not specified
15.0 - 20.0 Lacs P.A.
15.0 - 20.0 Lacs P.A.
Experience: Not specified
0.18 - 0.25 Lacs P.A.