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IBM
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NEST Lead - Functional Verification

NEST Lead - Functional Verification

IBM

10 - 15 years

6 - 10 Lacs

bengaluru

Posted:1 week ago| Platform:

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Skills Required

debugging continuous integration python ace c chi soc clock domain crossing stress testing uvm verilog scripting git devops system architecture computer architecture linux perl scripting languages programming unix architecture

Work Mode

Work from Office

Job Type

Full Time

Job Description

As a Functional verification engineer, you will be working on IBM server processors/SOC or

ASICs used in IBM servers.

Lead the development of the verification plans, environment, testbenches and writing

testcases for the system level in IBM Server Processors.

Develop skills in IBM Functional verification tools and methodologies.

Work with design as well as other key stakeholders in debugging and fixing logic design

issues and deliver a quality design

Work with development team to ensure coverage criteria is met

Required education

Master''s Degree

Preferred education

Bachelor''s Degree

Required technical and professional expertise

10+ years of experience in Functional Verification Lead of processors or ASICs.

5+ years of experience in the following areas

Computer architecture knowledge, Processor core design specifications, instruction

set architecture and logic verification.

Core architecture/micro-architecture verification

System level and unit level verification.

Multi-processor Cache Coherency/Network on Chip/Memory Hierarchy verification.

AXI/AHB/ACE/ACE-lite/CHI/On Chip System Fabric interface verification or any

other Processor/SoC coherency transport interconnect fabric verification.

Minimum one full life cycle leadership experience of a processor/SoC verification flow with
focus on Coherency Transport Interconnect and/or Network on Chip Verification

Strong object-oriented programming skills in C++/SystermVerilog, scripting languages like
Python/Perl.

Verification knowledge in Clock domain crossing and reset domain crossing

Knowledge of functional verification methodology like UVM/OVM

Knowledge of HDLs (VHDL/Verilog)

Developed test plans and test strategies for IP/unit/block level verification of Coherency Transport
Interconnects

Worked on multiple levels of verification (unit/element/sub-system/system level)

Development experience on Linux/Unix environments, GIT repositories and good
understanding of Continuous Integration and DevOps workflow

Exposure in developing testbench environment, write complex test scenario, debugging and
triaging fails

Experience in driving verification coverage closure.

Preferred technical and professional experience Additional skill preferences

Stress testing and ability to identify corner case scenarios and System level and unit level verification.

Good understanding of computer system architecture and microarchitecture.

Knowledge in IP Integration and SoC level verification.

Knowledge of design patterns in programming

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NEST Lead - Functional Verification