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Advanced Micro Devices, Inc
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MTS Silicon Design Engineer

MTS Silicon Design Engineer

Advanced Micro Devices, Inc

6 - 11 years

8 - 13 Lacs

bengaluru

Posted:1 day ago| Platform:

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Skills Required

static timing analysis soc analytical artificial intelligence perl budgeting gaming mts physical design recruitment

Work Mode

Work from Office

Job Type

Full Time

Job Description

THE ROLE:

The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology.

THE PERSON:

The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.

KEY RESPONSIBILITIES:

- RTL to GDS2 flow
- Working on Constraints, Full chip netlist generation, static timing analysis setup and signoff of multi-corner multi-voltage designs.
- Owning timing execution to meet timing requirements including timing budgeting, repeater planning, constraints/exceptions generation and management
- Areas of focus include Constraints generation, verification, Timing analysis and verification, extraction and noise glitch analysis
- Engaging closely with Design teams to understand the design, constraints and convergence challenges and providing ECOs with a focus on PPA and TAT optimizations.
- Hierarchical timing analysis and convergence at block, section and fullchip level.
PREFERRED EXPERIENCE:
- 6+ years of professional experience in Constraints generation, STA, full chip timing and physical design, preferably with high performance designs.
- Demonstrated ability in areas of Timing analysis, timing convergence, SI/Noise analysis, Signoff quality (PVT, process variation effects, guardbanding, etc), Timing ECOs, PV/Noise modelling, .libs, is a must.
- Multi-voltage scenarios design handling knowledge is expected. STA closure/convergence execution on Low power designs is an added advantage.
- Expertise in industry standard EDA tools (Primetime)
- Hands-on experience with Physical Design implementation is a plus
- Proficiency in scripting language, such as, Perl and Tcl.
- Versatility with scripts to automate design flow, analysis
- Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams
- Experience in 16/ 14/ 10/ 7/5nm nodes
- Good understanding of computer organization/architecture is preferred.
- Strong analytical/problem solving skills and pronounced attention to details.
ACADEMIC CREDENTIALS:
- Qualification: Bachelors or Masters in Electronics/Electrical Engineering

#LI-PK2

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MTS Silicon Design Engineer