Job
Description
Design and develop critical analog, mixed-signal, custom digital block and full chip level integration support. Responsible for layout verification tasks such as LVS/DRC/Antenna, quality check and documentation. Ensure on-time delivery of block-level layouts with acceptable quality. Contribute to effective project management. Communicate efficiently with engineering teams in the India, US, and Japan to ensure the success of the layout project. Have 1-3 years of experience in analog/custom layout design in advanced CMOS process. Expert in Cadence VLE/VXL and Calibre DRC/LVS. Have hands-on experience in Critical Analog Layout design of blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc. Have good understanding of Analog Layout fundamentals such as Matching, Electro-migration, Latch-up, coupling, cross-talk, IR-drop, active and passive parasitic devices etc. Understand layout effects on the circuit such as speed, capacitance, power and area etc. Ability to understand design constraints and implement high-quality layouts. Possess strong command and problem-solving skills in Physical layout verification. Have good understanding of basic active and passive devices such as R,L, C and MOSFETs. Scripting and automation experience is a plus but not mandatory. Have excellent verbal and written communication skills.
