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3.0 - 8.0 years
0 Lacs
karnataka
On-site
Role Overview: As an Analog & Mixed Signal Layout Engineer with 3-8 years of experience, you will be responsible for designing analog/custom layout in advanced CMOS process. Your expertise in tools like Cadence VLE/VXL, PVS, Assura, and Calibre DRC/LVS will be crucial for this role. You will be involved in critical analog layout design of various blocks such as Temperature sensor, Serdes, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier, etc. Your understanding of Analog Layout fundamentals and ability to implement high-quality layouts will be key to success in this position. Experience with multiple Tape out support will be an add...
Posted 1 day ago
5.0 - 7.0 years
0 Lacs
hyderabad, telangana, india
On-site
JobTitle : Layout/Mask Designer 3_INR Location : Bangalore Role and Responsibilities: Responsible for Design and development of critical analog, mixed-signal, custom digital block and full chip level integration support. Perform layout verification like LVS/DRC/Antenna, quality check and documentation. Responsible for on-time delivery of block-level layouts with acceptable quality. Contribute to effective project-management. Effectively communicating with engineering teams in the India, US, and Japan to assure the success of the layout project. Qualification/Requirements: 5-7 year experience in analog/custom layout design in advanced CMOS process. Expertise in Cadence VLE/VXL and Calibre DRC...
Posted 1 week ago
3.0 - 8.0 years
3 - 5 Lacs
bengaluru
Work from Office
1 Job Description for Memory Layout Location: Bangalore Experience : 3yrs-10 Yrs - Memory leaf cell layout development - Migration of layout from one tech node to another - Block and top level integration - Quality and timely delivery - EM-IR, area intensive layouts, Quality checks (QC) - Understanding of design rules for 90nm and below - Understanding of design rules for 14ff and 16ff is a plus. - Drive multiple projects and provide necessary technical guidance to the engineers - Understanding of DFM and DFY - Understanding of memory compiler architectures - Good debugging skills - Knowledge of scripting in PERL/Shell/TCL scripting etc - Proficient with tools like Cadence Virtuoso, Calibre ...
Posted 3 weeks ago
10.0 - 14.0 years
0 Lacs
karnataka
On-site
You are a Senior Principal Analog Layout Engineer at OnSemi, responsible for developing high-quality layout for complex AMS IP blocks including voltage regulators, bandgap, current sense-amp, amplifier, high voltage switches, and drivers. You will lead a team of 4-6 engineers, review their work, and drive continuous quality improvements. Your responsibilities include estimating schedules, managing manpower resources, and planning layout activities to ensure timely completion. In this role, you will contribute to area estimation, optimization, floor planning, power routing, shielding, and physical verification such as DRC, ERC, LVS, and ESD. Additionally, you will support the team in taping o...
Posted 2 months ago
8.0 - 12.0 years
0 Lacs
hyderabad, telangana
On-site
As a Non-Volatile Engineering (NVE) Product Engineer at Micron Technology, Inc., you will be a key player in the Mask Design Development team, contributing to the Design for Manufacturability (DFM) process for new designs. Your role involves ensuring the timely delivery of high-quality mask designs by collaborating with cross-functional teams, enhancing DFM capabilities, and improving design methodologies for better manufacturability and performance of NAND products. Your responsibilities will include integrating DFM best practices into the design process, developing and enhancing DFM capabilities and tools, providing feedback to the NAND Design team based on DFM and manufacturing experience...
Posted 3 months ago
1.0 - 3.0 years
2 - 4 Lacs
Hyderabad / Secunderabad, Telangana, Telangana, India
On-site
Design and develop critical analog, mixed-signal, custom digital block and full chip level integration support. Responsible for layout verification tasks such as LVS/DRC/Antenna, quality check and documentation. Ensure on-time delivery of block-level layouts with acceptable quality. Contribute to effective project management. Communicate efficiently with engineering teams in the India, US, and Japan to ensure the success of the layout project. Have 1-3 years of experience in analog/custom layout design in advanced CMOS process. Expert in Cadence VLE/VXL and Calibre DRC/LVS. Have hands-on experience in Critical Analog Layout design of blocks such as Temperature sensor, PLL, ADC, DAC, LDO, Ban...
Posted 4 months ago
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