IP Verification Engineer MTS/SDE

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD's graphics processor IP, resulting in no bugs in the final design.??

THE PERSON:

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.Experience requires demonstrated technical expertise in functional verification, test planning, test bench development, stimulus generation, checking, and functional coverage.Must demonstrate strong Object Oriented programing skills and concepts.Any experience with memory controllers, dfi, dram memory models(ddr4/5, lpddr4/5, hbm, NVDIMM) and/or ddr phys is a plus.

Requires strong communication skills and the ability to work independently as well as in a cross-site team environment.

KEY RESPONSIBILITIES:

1. Develop, maintain and enhance test environment/regression, and testbench.
2. Work on IP/blocktesting and debugging
3. Work on functional & code coverage, and performance/power testing.
4. Support SoC integration and bridge the gap between IP and SoC

PREFERRED EXPERIENCE:

• ASIC design verification experience with 8 to 11 years
• Hands on experience in developing complex UVC
• Good debugging skill and good knowledge of verification tool and methodology
• Hands on experience with coverage planning, coding, and coverage closure
• Should have worked on developing testplan at module level/IP level /Chip-level project
• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
• Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
• Estimate the time required to write the new feature tests and any required changes to the test environment
• Build the directed and random verification testsDebug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues?
• Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements

PREFERRED EXPERIENCE:

• Proficient in IP level ASIC verification
• Proficient in debugging firmware and RTL code using simulation tools?
• Proficient in using UVM testbenches and working in Linux and Windows environments
• Experienced with Verilog, System Verilog, C, and C++??
• Developing UVM based verification frameworks and testbenches, processes and flows
• Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
• Strong background in the C++ language, preferably on Linux with exposure to Windows platform
• Good understanding and hands-on experience in the UVM concepts andSystemVeriloglanguage
• Scripting language experience: Perl, Ruby,Makefile, shell preferred.??
• Exposure to leadership or mentorship is an asset

ACADEMIC CREDENTIALS:

• Bachelors orMastersdegree inECE, Electrical engineering degree or Master's degree preferred with emphasis in Electrical/Electronics Engineering. Preferred VLSI major in post-graduation