Hiring For Analog Design Engineer -Bangalore -NP- Immediate To 30days

Hi All,

Looking for skilled Analog Layout Engineer for our leading client at Bangalore location.

Total exp- 4 years to 10 years

Work Location-Bangalore

Notice Period- Immediate to 30 days

Skill-

• Analog Layout Design (Block/IP level)
• LVS/DRC Debugging
• FinFET Technology Node Experience (5nm, 7nm, 10nm, 14nm and below)
• EDA Tools
• Cadence Virtuoso Editor
• Calibre RVE
• Layout Optimization
• Area estimation
• Floorplanning
• Routing

JD

To work independently on block/IP levels analog layout design from schematic.

• Estimating the Area, Optimizing Floorplan, Routing and Verifications.
• Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below.
• Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts.
• Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally.

Role & responsibilities

• Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimization, routing, and layout verification.
• Perform LVS (Layout vs. Schematic) and DRC (Design Rule Check) debugging for advanced FinFET technology nodes (5nm, 7nm, 10nm, 14nm and below).
• Ensure layout quality by applying principles of matching, electromigration (EM), electrostatic discharge (ESD), latch-up prevention, shielding, parasitic management, and short channel effects.
• Utilize industry-standard EDA tools such as Cadence Virtuoso Editor and Calibre RVE for layout and verification tasks.

Preferred candidate profile

Interested candidates can drop the resume to sudebi.basu@orcapod.work