Full chip SoC timing lead

KEY RESPONSIBLITIES:

• Full chip level Die size estimation, Floor-planning, Power planning, IO planning, package compatibility, IO ring creation and ESD analysis
• Full chip Hierarchical planning, block planning , block level constraints, hierarchical clock tree implementation, block integration and chip finishing.
• Low power design with power estimation/optimization includingclock gating, power gating, power switch implementation and other low power techniques to reduce total power consumption.
• Full chip/Sub-system/Partition level Synthesis, Logic equivalence, implementation of low power UPF/CPF
• Full chip / sub-system level constraints, MMMC & cross talk aware timing closure with latest OCV based analysis
• RTL2GDSII design implementation and flow debug top down or bottoms up at chip level
• PPA (Power, Performance, Area and Schedule) closure and flow development for key IPs like CPU, Graphics, Multimedia, Fabric cores and/or other critical sub-systems
• Low Power signoff like Static and Dynamic power analysis at top level and/or sub-system level
• Full chip / sub system level Clock tree synthesis and advanced clock tree implementation.
• Top level ECO strategy for RTL, pre-physical and post-route implementation considering timing, congestion and logic equivalence
• Physical design and timing methodology development on a particular node as well as for a specific SOC
• Automation to improve design PPA (Power, Performance, Area) and ensure a high-quality design environmentfor an SOC
• Hands-on in reference flows, excellent debugging skills.
• Experience in 5nm & below technologies.

PREFERRED EXPERIENCE:

• Minimum14+ years of relevantwork experience.
• Expertise in ICC2/ FC (Fusion Compiler) Physical Design flows/methodologies or equivalent tools.
• Expertise in Signoff tools like Primetime for Timing, Calibre for DRC/LVS, Ansys Redhawk on EMIR, PT-PX for Power signoff
• Should have worked as a go to person or technical lead for at least few full chip projects.
• Strong technical leadership and ability to mentor/guide/coach design engineers to achieve and deliver project goals.
• Strong inter-personal skills and ability to collaborate with teams spread across multiple geos.
• Should have good scripting experience in Shell, Python, Perl, TCL, UNIX along with decode/debug old existing scripts.

ACADEMIC CREDENTIALS:

• Bachelors orMaster'sdegree in Computer/Electronics/Electrical Engineering