FPGA IP Verification Engineer

Designs, develops, validates, and/or debugs software abstractions and frameworks for acceleration with FPGAs to support embedded, data center, and communication clients.

Key Responsibilities

• Collaborate with architects and design engineers to understand IP specifications and define comprehensive verification strategies and detailed test plans.
• Develop robust, reusable, and constrained-random verification environments using

  SystemVerilog

  and

  UVM (Universal Verification Methodology)

  .
• Create and implement directed and random test cases and test sequences to exercise design functionality and uncover potential bugs.
• Develop verification components, including drivers, monitors, scoreboards, and checkers.
• Utilize

  SystemVerilog Assertions (SVA)

  and formal verification methods to enhance bug detection and verify complex properties.
• Execute simulation regressions, debug test failures, analyze root causes, and work with designers to implement corrective measures.
• Define and track functional and code coverage metrics to ensure verification completeness and drive coverage closure.
• Develop automation scripts and infrastructure using languages like

  Python

  or

  Perl

  to improve verification efficiency and flows.
• Participate in technical reviews of specifications, design documents, and test plans, providing valuable input and feedback.

Qualifications:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of experience in ASIC or FPGA design verification.
• Expertise in Hardware Description Languages (HDL) like

  Verilog

  or VHDL and Hardware Verification Languages (HVL) such as

  SystemVerilog

  .
• Strong hands-on experience in developing UVM-based testbenches and verification components.
• Proficiency in modern verification methodologies, including coverage-driven verification (CDV) and assertion-based verification (ABV).
• Familiarity with industry-standard protocols such as

  AMBA (AXI, ACE, CHI, APB)

  , PCIe, or Ethernet is a plus.
• Experience with simulation and debug tools (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa).
• Strong scripting skills in

  Python

  ,

  Perl

  , or Tcl for automation and data analysis.
• Excellent analytical, problem-solving, and debugging skills.
• Strong communication skills and the ability to work effectively in a collaborative, cross-functional team environment.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.