Posted:5 days ago|
Platform:
On-site
Full Time
Experience-5-8Yrs
RTL FPGA design experience with Verilog, VHDL & System Verilog .
experience in Xilinx FPGA Design.
Design experience with Xilinx Vivado & ILA Hardware Debugger.
Good understanding of FPGA architecture and MMCM clock structure.
Experience with Ultrascale FPGA devices is a plus.
Proficiency in clock gating and FPGA timing closer techniques.
Mirafra Technologies
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