FPGA and RTL Design Engineer

Location:

About the Role

We are looking for a seasoned RTL/FPGA Design Engineer with a strong background in wireless communication systems, particularly 4G/5G and ORAN architectures. The ideal candidate will have hands-on experience in designing and implementing FPGA-based solutions for radio and baseband processing, and will contribute to the development of next-generation wireless infrastructure.

Key Responsibilities

• Design, implement, and verify RTL modules for wireless communication systems using Verilog/VHDL/SystemVerilog.
• Develop FPGA-based solutions for radio signal processing, fronthaul interfaces, and ORAN-compliant architectures.
• Collaborate with system architects and software teams to define hardware-software partitioning and optimize performance.
• Integrate and validate 4G/5G physical layer components on FPGA platforms (Xilinx, Intel/Altera, etc.).
• Perform timing analysis, synthesis, and place-and-route using industry-standard EDA tools.
• Support lab bring-up, debugging, and validation of FPGA designs with real-time radio hardware.
• Document design specifications, test plans, and verification results.

Required Skills & Qualifications

• Bachelors or Masters degree in Electrical/Electronics Engineering,
• 5+ years of experience in RTL/FPGA design and verification.
• Strong understanding of 4G/5G wireless protocols, physical layer processing, and radio systems.
• Experience with ORAN architecture, including fronthaul (eCPRI, CPRI), DU/RU split, and timing synchronization.
• Proficiency in Verilog/VHDL/SystemVerilog and FPGA development tools (Vivado, Quartus, ModelSim, etc.).
• Familiarity with high-speed interfaces (PCIe, JESD204B/C, Ethernet) and memory protocols (DDR, HBM).
• Hands-on experience with lab equipment (oscilloscopes, spectrum analyzers, signal generators) for RF validation.

Preferred Qualifications

• Experience with Xilinx Zynq Ultrascale+ or Intel Stratix platforms.
• Knowledge of embedded systems and integration with ARM cores or soft processors.
• Exposure to MATLAB/Simulink for algorithm modeling and verification.
• Familiarity with scripting languages (Python, TCL) for automation and testbench development.