Formal Verification Lead Engineer, Silicon

You will be part of a team that is focused on developing custom silicon solutions for Google's direct-to-consumer products. Your work will contribute to the innovation behind products that are loved by millions worldwide. Your expertise will be instrumental in shaping the next generation of hardware experiences, ensuring unparalleled performance, efficiency, and integration. - Collaborate with hardware architects to formalize specifications and verify system-level properties. - Create highly abstract models of different designs and ensure architectural correctness within a model and consistency across models. - Design formal verification strategies, establish properties and constraints for complex digital design blocks. - Translate system-level formal specifications into precise constraints for individual logical blocks. - Architect and deploy reusable formal verification components. - Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. - 8 years of experience with formal model checking for ASICs and FPGAs, SystemVerilog, and SystemVerilog Assertions. - Experience with formal verification EDA tools. - Experience with model checking frameworks such as Murphi or TLA+. Preferred Qualifications: - Master's or PhD degree in Computer Science, Electrical Engineering, or a related field. - Experience working with formal verification tools like JasperGold, VC Formal, Questa Formal, 360-DV. - Proficiency in a scripting language such as Perl, Tcl, or Python. - Familiarity with propositional logic, theorem proving, and tools like Z3.,