8.0 - 12.0 years

0 Lacs

karnataka

On-site

As a Senior Formal Verification Engineer specializing in CPUs, you will be responsible for the property-based formal verification of the CPU core, pipeline stages, and subcomponents with exhaustive proof goals. Your role will involve leading formal planning and methodology for control logic, pipelines, and memory subsystems. You will define safety and liveness properties, model check for corner case behavior, and guide designers in writing formal-friendly RTL and assertions. Additionally, you will analyze convergence issues, coverage gaps, and create abstraction models, while integrating formal sign-off into project milestones. To excel in this role, you should have a minimum of 8 years of formal verification experience with CPUs or processors. Proficiency in tools such as JasperGold, VC Formal, OneSpin, or equivalent is required. Expertise in SVA/PSL, abstraction modeling, and formal coverage closure is essential. A strong background in computer architecture, particularly in pipeline, MMU, and interrupt logic, will be beneficial. You should possess excellent problem-solving skills, convergence debugging abilities, and strong documentation skills. If you meet these requirements and are interested in this opportunity, please submit your updated CV to janagaradha.n@acldigital.com.,

Posted 1 week ago

Apply

Formal Verification Engineer Kaizen SRA Technologies Private Limited

6.0 - 15.0 years

4 - 15 Lacs

Hyderabad / Secunderabad, Telangana, Telangana, India

On-site

Job Title : Formal Verification Engineer Experience range : 6-15 Yrs Location : Hyderabad Availability : Immediate 30 days Job Description : Responsibilities : Identify blocks suitable for applying Formal Verification Create Formal Test-plan for blocks identifying properties to be implemented and sign-off metrics. Implementation and maintenance of Formal Verification environments in Chisel Applying various FV techniques to reduce complexity and prove correctness of DUT. Debugging RTL to identify causes of failure scenarios. Guide and train team members on effective usage of Formal Verification tools Develop/modify scripts to automate the verification process. Review formal setups and proofs with design and verification teams. Maintain and extend assertion libraries. 7+ years of experience in Formal Verification of Digital Hardware Design Extensive experience with Formal Abstraction Techniques and sign-off process Familiarity with industry-standard Formal Verification Tools, such as VC Formal, Jasper Gold Knowledge of Hardware Description and Verification Languages, such as VHDL, Verilog/ System Verilog Knowledge of Object-oriented Programming is a plus. A keen interest in Processors and Digital systems Strong reasoning skills and excellent attention to detail Good interpersonal and teamwork skills!

Posted 2 months ago

Apply

Staff Formal Verification Engineer Mulya Consulting

7 - 12 years

40 - 75 Lacs

Bengaluru

Work from Office

Staff Silicon Formal Verification Engineer :- Bangalore Founded in 2023,by Industry veterans HQ in California,US We are revolutionizing sustainable AI compute through intuitive software with composable silicon Silicon Formal Verification Engineer Job Description In this role you will be responsible for developing and applying formal verification techniques to ensure functional correctness and completeness of high performance AI/ML Chiplet and SiP products. You will collaborate with a team of highly skilled team Architects and RTL Design engineers to identify, define, and verify components suited for formal analysis. Create robust formal abstract models to verify system-level properties, such as deadlocks, livelocks, anti-starvation, coherency. Innovate by integrating formal methods with simulation-based techniques to enhance bug detection efficiency. Develop scalable and reusable proof methodologies to support the verification process. Technical Requirements In-depth knowledge in formal verification algorithms, methods and use cases Expert user of formal verification tools (JasperGold, VC Formal, Questa Formal tools) Expertise in system Verilog assertion and abstract model development Hands on experience as Formal verification Engineer on AI or CPU designs. Comprehensive knowledge of computer architecture and familiarity with x86 or ARM or RISC processors:- Job Description In this role you will be responsible for developing and applying formal verification techniques to ensure functional correctness and completeness of high performance AI/ML Chiplet and SiP products. You will collaborate with a team of highly skilled team Architects and RTL Design engineers to identify, define, and verify components suited for formal analysis. Create robust formal abstract models to verify system-level properties, such as deadlocks, livelocks, anti-starvation, coherency. Innovate by integrating formal methods with simulation-based techniques to enhance bug detection efficiency. Develop scalable and reusable proof methodologies to support the verification process. Technical Requirements In-depth knowledge in formal verification algorithms, methods and use cases Expert user of formal verification tools (JasperGold, VC Formal, Questa Formal tools) Expertise in system Verilog assertion and abstract model development Hands on experience as Formal verification Engineer on AI or CPU designs. Comprehensive knowledge of computer architecture and familiarity with x86 or ARM or RISC processors Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"

Posted 2 months ago

Apply

Start Your Job Search Today

Browse through a variety of job opportunities tailored to your skills and preferences. Filter by location, experience, salary, and more to find your perfect fit.