6 Questa Formal Jobs

Position Overview We are looking for a Lead Engineer in SoC Verification to join our team and contribute to the Formal Property Verification (FPV) and Connectivity Verification of complex SoC designs. The engineer will be responsible for developing, executing, and maintaining formal verification strategies to ensure exhaustive property coverage, structural correctness, and architectural compliance across critical blocks and subsystems. This role requires strong expertise in formal methodologies, hands-on experience with industry-standard formal tools, and the ability to collaborate closely with RTL design, architecture, and full-chip verification teams to ensure first-pass silicon success. T...

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more efficiently. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. Customers around the world trust in our products and our application engineers significantly contribute to that. You are the first on the scene to address any technical problem. You are a competent adviser, great teammate, and make things possible. Unsolvable is a foreign term, and you don't do unfair. Your foc...

You will be part of a team that is focused on developing custom silicon solutions for Google's direct-to-consumer products. Your work will contribute to the innovation behind products that are loved by millions worldwide. Your expertise will be instrumental in shaping the next generation of hardware experiences, ensuring unparalleled performance, efficiency, and integration. - Collaborate with hardware architects to formalize specifications and verify system-level properties. - Create highly abstract models of different designs and ensure architectural correctness within a model and consistency across models. - Design formal verification strategies, establish properties and constraints for c...

Job Title: Formal Verification Engineer Location: Bangalore Experience: 4+Years Job Type: Full-time Industry: Semiconductor / ASIC Design / EDA Education: B.E./B.Tech or M.E./M.Tech in ECE/EEE/Computer Engineering Job Description: We are looking for a highly motivated Formal Verification Engineer to join our Design Verification team. The candidate will be responsible for developing and executing formal verification strategies to ensure functional correctness of complex IP and SoC designs. Key Responsibilities: Define and implement formal verification strategies and plans. Develop formal properties and assertions for critical design blocks. Apply formal techniques such as property checking, s...

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. 1 years of experience with verification methodologies and languages (e.g., Universal Verification Methodology, SystemVerilog). Experience developing and maintaining verification testbenches, test cases, and test environments. Experience working on main interconnects, Direct Memory Access (DMA), controllers, power management, and capturing design specifications in a temporal assertion language (e.g., System Verilog Assertions (SVA) or Property Specification Language (PSL)). Preferred qualifications: Master's degree or PhD in Electrical Engineering or Computer Science. Exp...

Staff Silicon Formal Verification Engineer :- Bangalore Founded in 2023,by Industry veterans HQ in California,US We are revolutionizing sustainable AI compute through intuitive software with composable silicon Silicon Formal Verification Engineer Job Description In this role you will be responsible for developing and applying formal verification techniques to ensure functional correctness and completeness of high performance AI/ML Chiplet and SiP products. You will collaborate with a team of highly skilled team Architects and RTL Design engineers to identify, define, and verify components suited for formal analysis. Create robust formal abstract models to verify system-level properties, such...