About The Role

Conducts verification of IP and/or SoC microarchitecture using formal verification tools, methodologies, and technologies based on model checking and equivalence checking algorithms.

Creates comprehensive formal verification test and coverage plans including definition of formal verification scope, strategy, and techniques.

Creates abstraction models for convergence on the design, carves out the right boundaries for the design, and tracks, verifies, and applies abstraction techniques.

Develops formal proofs to implement the verification plan, reviews the completed proofs, and develops new formal verification methodologies.

Performs convergence on design by creating formal verification methodology, abstraction, and simulation techniques.

Finds and implements corrective measures to resolve failing tests.

Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.

Documents test plans and drives technical reviews of plans.

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications:

5+ years of experience in the verification of IPs

Hands on experience in applying formal property verification for Ips signoff at least for 3 years

Hands on experience in resolving convergence issues using FV on multiplies

Managing and Guiding juniors in their verification task, Stakeholder management.

Preferred Qualifications:

Expertise in FV verification planning and strategies

Good understanding of FV tools and capabilities