Engineer, ASIC Verification

As a part of Kinara, a Bay Area-based venture backed company, your role will involve developing verification environments for modules, subsystems, top level, and FPGA. You will be responsible for building models, checkers, and random test frameworks using SystemVerilog and UVM. Additionally, you will participate in Low power analysis (UPF), power estimation, and C modeling. Your tasks will also include performing lint, CDC, code coverage, functional coverage, and formal verification of modules using SVA assertions. Key Responsibilities: - Develop verification environments for modules, subsystems, top level, and FPGA - Build models, checkers, and random test frameworks using SystemVerilog and UVM - Participate in Low power analysis (UPF), power estimation, C modeling - Perform lint, CDC, code coverage, functional coverage - Formal verification of modules using SVA assertions Qualifications Required: - Experience in verifying complex subsystems and ASICs - Experience with building scalable verification environments from scratch - Proficient at Verilog, UVM, EDA tools, scripting, automation, build, regression systems etc. - Exposure to FPGA emulation platforms, silicon bringup, board debug - BTech/MTech in EE/CS with any level of experience Kinara fosters innovation and provides an environment where every team member's viewpoint is valued. As part of the team, you will have access to technology experts and mentors who will guide and coach you to work on exciting challenges. If you are passionate about making a difference in the field of edge AI, Kinara welcomes you to join them in creating a smarter, safer, and more enjoyable world. Make your mark by applying today!,