ASIC RTL (DSP) Design Engineer/Sr Lead/Staff/Sr Staff Qualcomm

1.0 - 5.0 years

0 Lacs

karnataka

On-site

As an experienced RTL designer, you will be responsible for working on complex high-performance RTL design, with a focus on DSP or processor-based sub-systems. Your expertise in hardware design using Verilog, System Verilog, or VHDL, along with knowledge of on-chip bus interface protocols such as AXI, APB, and AHB, will be essential for success in this role. Additionally, your experience with model development, RTL to gate synthesis, design rule checking, and scripting languages will be valuable assets. Key Responsibilities: - Develop micro-architecture, design, and program specific documentation - Design and model compute ASIC modules and sub-systems - Own RTL development, ensuring power, p...

Posted 1 month ago

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Engineer, ASIC Verification kinara

0.0 - 4.0 years

0 Lacs

hyderabad, telangana

On-site

As a part of Kinara, a Bay Area-based venture backed company, your role will involve developing verification environments for modules, subsystems, top level, and FPGA. You will be responsible for building models, checkers, and random test frameworks using SystemVerilog and UVM. Additionally, you will participate in Low power analysis (UPF), power estimation, and C modeling. Your tasks will also include performing lint, CDC, code coverage, functional coverage, and formal verification of modules using SVA assertions. Key Responsibilities: - Develop verification environments for modules, subsystems, top level, and FPGA - Build models, checkers, and random test frameworks using SystemVerilog and...

Posted 2 months ago

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ASIC RTL (DSP) Design Engineer/Sr Lead/Staff/Sr Staff Qualcomm

1.0 - 5.0 years

0 Lacs

karnataka

On-site

Qualcomm India Private Limited is seeking a Hardware Engineer with expertise in complex high-performance RTL design, particularly on DSP or processor based sub-systems. You should be proficient in hardware design using Verilog, System Verilog, or VHDL and have knowledge of on-chip bus interface protocols like AXI, APB, and AHB. Experience in model development (SystemC, or C++), RTL to gates synthesis (Synopsys DCG or Cadence Genus), design rule and CDC checking (SVA assertions, Spyglass, 0-in), and working on high-performance low power RTL design is essential. Familiarity with scripting languages such as PERL, Python, TCL, C, etc., is also required. As a Hardware Engineer at Qualcomm, your r...

Posted 4 months ago

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