Design Verification (Asic Verification)

You are seeking Senior DV engineers for BLR location with 6+ years of experience in SoC Verification. As a Senior DV engineer, your responsibilities will include developing Detailed Documentation for Verification Strategy and Test Plan for IP, Subsystem, and SoC. You will be involved in Directed and Random Verification at IP, Subsystem, and SoC Level for complex ARM / RISC-V processor based MCU, MPU products, Mixed Signal SoCs, Processors, Memory Subsystems, Connectivity Platforms, Analog, Security Acceleration, General Peripherals. Additionally, you will perform Functional and Code Coverage Analysis. To qualify for this position, you should have 6 to 15 years of experience in SoC Verification and expertise in Verilog, System Verilog, UVM, Constrained Random Verification, Formal Verification, Mixed Signal Verification, Post-Layout Gate Level Simulations, Code Coverage, and Functional Coverage analysis. You must also possess strong expertise in DDR, LPDDR, Pcie, Ethernet, USB Protocols (Any One). Strong debug and analytical capabilities, as well as in-depth understanding of SoC Design Flow, RTL Implementation, and Analog Circuit models, are essential for this role. Soft skills required for this position include strong analytical, problem-solving, and hands-on skills. You should be self-driven and thrive when facing open-ended tasks. A start-up mentality with a fast-paced, flexible, and team-oriented approach is desirable. Good written and verbal communication skills with great documentation skills are crucial. Flexibility to work with varied schedules and tolerance for ambiguity are also necessary attributes. If you meet the requirements and are interested in this opportunity, kindly share your updated profile with anand.arumugam@modernchipsolutions.com.,