Design Verification (Asic Verification) Modernize Chip Solutions (MCS)

6.0 - 15.0 years

0 Lacs

karnataka

On-site

You are seeking Senior DV engineers for BLR location with 6+ years of experience in SoC Verification. As a Senior DV engineer, your responsibilities will include developing Detailed Documentation for Verification Strategy and Test Plan for IP, Subsystem, and SoC. You will be involved in Directed and Random Verification at IP, Subsystem, and SoC Level for complex ARM / RISC-V processor based MCU, MPU products, Mixed Signal SoCs, Processors, Memory Subsystems, Connectivity Platforms, Analog, Security Acceleration, General Peripherals. Additionally, you will perform Functional and Code Coverage Analysis. To qualify for this position, you should have 6 to 15 years of experience in SoC Verification and expertise in Verilog, System Verilog, UVM, Constrained Random Verification, Formal Verification, Mixed Signal Verification, Post-Layout Gate Level Simulations, Code Coverage, and Functional Coverage analysis. You must also possess strong expertise in DDR, LPDDR, Pcie, Ethernet, USB Protocols (Any One). Strong debug and analytical capabilities, as well as in-depth understanding of SoC Design Flow, RTL Implementation, and Analog Circuit models, are essential for this role. Soft skills required for this position include strong analytical, problem-solving, and hands-on skills. You should be self-driven and thrive when facing open-ended tasks. A start-up mentality with a fast-paced, flexible, and team-oriented approach is desirable. Good written and verbal communication skills with great documentation skills are crucial. Flexibility to work with varied schedules and tolerance for ambiguity are also necessary attributes. If you meet the requirements and are interested in this opportunity, kindly share your updated profile with anand.arumugam@modernchipsolutions.com.,

Posted 6 days ago

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Senior FPGA Engineer Black Box

5.0 - 9.0 years

0 Lacs

karnataka

On-site

You will be joining as a Senior FPGA Engineer professional at our Bangalore location with a minimum of 5 years of experience. In this role, your primary responsibilities will include collaborating with a team of product managers, developers, and testers to define feature requirements, developing feature specifications, and implementing detailed designs using Verilog and FPGA design tools. You will also be involved in problem isolation, fault finding in embedded systems, customer issue replication, and creating/updating release notes. Additionally, you will work closely with onsite and offsite development teams to deliver market-leading products globally and mentor junior engineers in development, code, and debugging. To excel in this role, you must be an expert Verilog/System Verilog developer with strong embedded debugging skills. Proficiency in AMD/Xilinx FPGA with Vivado/Vitis tool-chains for implementations and validation, as well as experience with Xilinx/AMD simulator/ModelSim for unit and system-level simulations, is essential. You should possess excellent analytical skills, adaptability to ambiguity and change, and a thorough understanding of the FPGA development cycle within project-based environments. Experience with modern 32-bit processors/microcontrollers like ARM, debuggers, protocol analyzers, and logic analyzers is required. Desirable skills include expertise in Embedded Linux Kernel and Device Drivers development, familiarity with video and audio codecs such as MPEG4 and JPEG, knowledge of USB protocols, and understanding of network protocol stack concepts like ethernet, IP, and TCP. Strong communication and documentation skills are necessary for this role. If you are interested in this opportunity, please share the following details along with your profile to vijitha.k@blackbox.com: - Total experience: - Relevant experience in FPGA: - Experience in Embedded: - Experience in Linux: - Current CTC: - Expected CTC: - Notice period: - Current Location: - Preferred Location: - Current Company: - Any pending offers: - Educational Qualifications,

Posted 1 month ago

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